From patchwork Thu Jul 14 16:15:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 12918176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 956A6C43334 for ; Thu, 14 Jul 2022 16:16:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ukaSWQlrV7Q5ZU3tnumyfbsvHRi9dqCtzwR1f8Dyy3k=; b=i4d0M1cs0jEFE3 +Ws5bdm5g+vtu6IAd42ZlFNU4ZtcFqNTJbnBTfcW5vnVH/7A25BwLf2NzHnvemv9w67z0I71CP154 lYOYKnp10XDgwqUDB82+XA8zXHtRZOlneuv7QQ7OAU/v1Kx5RYbT5nVSDz9J5g3sLgCfHTMO+lz1j Yv4UbkBTBi7lBhyojMy5HpKMM2lY+L7Lc+ZojMZabhcKsxQNdB32Dr+mz7d/gGC0vge0g25jYELp6 AeprscbtoiD83icPQdtDS0rktETbBlOvN0YMYHuw092ECJLwTbqsWiiymkg8hW/0xNQi8en2MIXtP fEPrZGduvBPjG4T7VS1w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oC1V5-00G9To-3R; Thu, 14 Jul 2022 16:15:39 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oC1Uz-00G9Pj-PF for linux-arm-kernel@lists.infradead.org; Thu, 14 Jul 2022 16:15:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3335F1D14; Thu, 14 Jul 2022 09:15:33 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.174]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D79D33F70D; Thu, 14 Jul 2022 09:15:31 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Russell King , Catalin Marinas , Will Deacon , Ard Biesheuvel , James Morse Subject: [PATCH v3 1/2] ARM: Remove AES hwcap for parts affected by errata Date: Thu, 14 Jul 2022 17:15:22 +0100 Message-Id: <20220714161523.279570-2-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714161523.279570-1-james.morse@arm.com> References: <20220714161523.279570-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220714_091533_918127_777550C6 X-CRM114-Status: GOOD ( 14.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Cortex-A57 and Cortex-A72 have an erratum where an interrupt that occurs between a pair of AES instructions in aarch32 mode may corrupt the ELR. The task will subsequently produce the wrong AES result. The AES instructions are part of the cryptographic extensions, which are optional. User-space software will detect the support for these instructions from the hwcaps. If the platform doesn't support these instructions a software implementation should be used. Remove the hwcap bits on affected parts to indicate user-space should not use the AES instructions. A57's r0p0 is not affected, add a read_cpuid_variant() helper and check the revision and variant. Acked-by: Ard Biesheuvel Signed-off-by: James Morse --- arch/arm/include/asm/cputype.h | 5 +++++ arch/arm/kernel/setup.c | 10 ++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 775cac3c02bb..5b28611ed459 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -223,6 +223,11 @@ static inline unsigned int __attribute_const__ read_cpuid_implementor(void) return (read_cpuid_id() & 0xFF000000) >> 24; } +static inline unsigned int __attribute_const__ read_cpuid_variant(void) +{ + return read_cpuid_id() & 0x00f00000; +} + static inline unsigned int __attribute_const__ read_cpuid_revision(void) { return read_cpuid_id() & 0x0000000f; diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 1e8a50a97edf..470fa860cd7d 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -501,6 +501,16 @@ static void __init elf_hwcap_fixup(void) return; } + /* + * HWCAP2_AES can get the wrong result due to A57's erratum #1742098 or + * A72's #1655431. A57 r0p0 is not affected. + */ + if ((read_cpuid_part() == ARM_CPU_PART_CORTEX_A57 && + read_cpuid_variant() != 0 && read_cpuid_revision() != 0) || + read_cpuid_part() == ARM_CPU_PART_CORTEX_A72) { + elf_hwcap2 &= ~HWCAP2_AES; + } + /* Verify if CPUID scheme is implemented */ if ((id & 0x000f0000) != 0x000f0000) return;