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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: b9gwg1w3CJuNxYyWfN+zyUldetLQPIJ4fR26VbvTsXhwxhG3I3e/DIoKebhl3tFrDzW2NTcAAZox/j+D+zAVhBorjtD2HuZbgoSzx0d24dk6FbbMzoJc7pKACLxBXT3f/Gz93za2f+m54su5io6T+x7K5SLvshQjJrxfwAK/e0LrK4q2qnU55EMEW5n4nOIo3lXGvxu7ZGHl5OQyBtNxiNMLdDAPLqIOtDjt3DWlqgFdDhpymEIeXjQ9JnkoP4tXYDKHzxL/L8yIpHHPdgcI5FmUky1vpjPoSPe0l1F+l61EUcrujRaoTtI8lfJhggX/7C1YKAIywMPQUUVoBZvsSDPijIAQP6kb6VPPS9dlhTix1wsyyI0+C7/G2ykyqzOZ1PM+hsIjr9qcxWSx5flq+DtQyvtLZ3KTaevlibjLlrjlIDvENSveqnEjKsu9CIx2wkQmKctCFBFMR0qGZr8oaHXogoEMqd3m8OFKR5scdd4/9SlcUSjtCGnZMR7kssyggN5tut6bJEek77vDtt5Qgb+D5HgokFU/it5Etq7dJkt/fPXwsfvBowHfgjctO78frAIeBYd56f+OMk2uQTIFHAPLIpBwoBb+B7wjs3stHYkBh5nV/l7c6u8waIFsAHR5gjWNvfAo8RCBvtZ/prVYAYE/t4tD5e6KejyMN9EP/GtEMDDsus5hMGCzx/7UYOAWjCbEjH1PRdMjCfNSMqUgVAXyWEosVcv1SgrdmrgZu5HJ8PK6hi1skDtTPr6iAPI2HHexAY68pR+D1NcqfVqCLnkMv21BkVBMQQOT6Dia1xcxkMIfvY4KBYFVhExVy9HgD76sXAGueP9yQMTXiO0HlgWy1C7imEW247WGdoCHIqeqWIxGMJKRUvgiXxxVnq6lN8PKZ0+zXmvyWoV/PMox2SzPxYu4uIC3mR0TPuyNRHLr3BNKSJXrcKWmUOHwL9wqKPxdtKtRTseJYDDc1EC7JOsBKQGIsBMOILrCnVksJtDlHqiAyaS5yrm7+S8E+kG+2L7ZH3ZLon8MmAch55sRKFezaRz2oN8ISt1HHQRh8H4TMpDc6nifCgKrRPUy+jp9RfmKftI732rVXrjRddb7yW7Q4ENFbmNd1VykZXSI/+MCa/SftQw2bdGsg+mbnmFJ6XTBnLi+/BONkp81vrvbQcO6K+jUt0ojTvGGddA6cwldpuq7uQqXtoo9X7iRxysuAxNtSHp7dVVHL78Ncrx8HL5CD8M6t+D4PVhaEdkE14xeEzAy0OTayM/SWQF5+6+Ybo7ZmHzTtwX4CCXYyBbammMTYh6fgnWELogklGPaG0h+xpW8EkA5OV3zIoq4DMJGG23Wme4IPKXim2PudWLN1LankGoBob5VvjH3M7u1eyzx3v1VPJsyZkH3t7DQDPaGijumAcSsJ/m1fWhQtaqHPupsZIoC3T9xa7KtVAq2WD9m2irVuuTPjYeOnvl1TQsNqSlQp50XXIACmlmMS6KuuzgpPMjCFtQ9w8KKkXhSfHSDtOjQiAGkWYE0n2UT7aGSo/PaF16aRD5aj2ijkwlBmon7VBjB/gV5M72x+RDQmjRc4VYvOtkIcmH9bDLN+CY29FYzIBLC2GcDKX4QlSGnng== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 01cd95de-de2b-474f-38a4-08da67843f83 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2022 23:38:12.6660 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iKGqncZgILZ4kbb00KFZ4B368mOElVjKgR3v6ojUlZGveNDEtkkTBBh9+y3GPU91Iq/6zJExQckcCfBMM+Er9g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB3997 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220716_163820_582618_08BA886C X-CRM114-Status: GOOD ( 16.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The irqchip->irq_set_type method is called by __irq_set_trigger() under the desc->lock raw spinlock. The armada-37xx implementation, armada_37xx_irq_set_type(), takes a plain spinlock, the kind that becomes sleepable on RT. Therefore, this is an invalid locking scheme for which we get a kernel splat stating just that ("[ BUG: Invalid wait context ]"), because the context in which the plain spinlock may sleep is atomic due to the raw spinlock. We need to go raw spinlocks all the way. Replace the driver's irq_lock with a raw spinlock, to disable preemption even on RT. Fixes: 2f227605394b ("pinctrl: armada-37xx: Add irqchip support") Signed-off-by: Vladimir Oltean --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 38 ++++++++++----------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index a140b6bfbfaa..8fddc67271b4 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -102,7 +102,7 @@ struct armada_37xx_pinctrl { struct device *dev; struct gpio_chip gpio_chip; struct irq_chip irq_chip; - spinlock_t irq_lock; + raw_spinlock_t irq_lock; struct pinctrl_desc pctl; struct pinctrl_dev *pctl_dev; struct armada_37xx_pin_group *groups; @@ -523,9 +523,9 @@ static void armada_37xx_irq_ack(struct irq_data *d) unsigned long flags; armada_37xx_irq_update_reg(®, d); - spin_lock_irqsave(&info->irq_lock, flags); + raw_spin_lock_irqsave(&info->irq_lock, flags); writel(d->mask, info->base + reg); - spin_unlock_irqrestore(&info->irq_lock, flags); + raw_spin_unlock_irqrestore(&info->irq_lock, flags); } static void armada_37xx_irq_mask(struct irq_data *d) @@ -536,10 +536,10 @@ static void armada_37xx_irq_mask(struct irq_data *d) unsigned long flags; armada_37xx_irq_update_reg(®, d); - spin_lock_irqsave(&info->irq_lock, flags); + raw_spin_lock_irqsave(&info->irq_lock, flags); val = readl(info->base + reg); writel(val & ~d->mask, info->base + reg); - spin_unlock_irqrestore(&info->irq_lock, flags); + raw_spin_unlock_irqrestore(&info->irq_lock, flags); } static void armada_37xx_irq_unmask(struct irq_data *d) @@ -550,10 +550,10 @@ static void armada_37xx_irq_unmask(struct irq_data *d) unsigned long flags; armada_37xx_irq_update_reg(®, d); - spin_lock_irqsave(&info->irq_lock, flags); + raw_spin_lock_irqsave(&info->irq_lock, flags); val = readl(info->base + reg); writel(val | d->mask, info->base + reg); - spin_unlock_irqrestore(&info->irq_lock, flags); + raw_spin_unlock_irqrestore(&info->irq_lock, flags); } static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) @@ -564,14 +564,14 @@ static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) unsigned long flags; armada_37xx_irq_update_reg(®, d); - spin_lock_irqsave(&info->irq_lock, flags); + raw_spin_lock_irqsave(&info->irq_lock, flags); val = readl(info->base + reg); if (on) val |= (BIT(d->hwirq % GPIO_PER_REG)); else val &= ~(BIT(d->hwirq % GPIO_PER_REG)); writel(val, info->base + reg); - spin_unlock_irqrestore(&info->irq_lock, flags); + raw_spin_unlock_irqrestore(&info->irq_lock, flags); return 0; } @@ -583,7 +583,7 @@ static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) u32 val, reg = IRQ_POL; unsigned long flags; - spin_lock_irqsave(&info->irq_lock, flags); + raw_spin_lock_irqsave(&info->irq_lock, flags); armada_37xx_irq_update_reg(®, d); val = readl(info->base + reg); switch (type) { @@ -607,11 +607,11 @@ static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) break; } default: - spin_unlock_irqrestore(&info->irq_lock, flags); + raw_spin_unlock_irqrestore(&info->irq_lock, flags); return -EINVAL; } writel(val, info->base + reg); - spin_unlock_irqrestore(&info->irq_lock, flags); + raw_spin_unlock_irqrestore(&info->irq_lock, flags); return 0; } @@ -626,7 +626,7 @@ static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info, regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l); - spin_lock_irqsave(&info->irq_lock, flags); + raw_spin_lock_irqsave(&info->irq_lock, flags); p = readl(info->base + IRQ_POL + 4 * reg_idx); if ((p ^ l) & (1 << bit_num)) { /* @@ -647,7 +647,7 @@ static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info, ret = -1; } - spin_unlock_irqrestore(&info->irq_lock, flags); + raw_spin_unlock_irqrestore(&info->irq_lock, flags); return ret; } @@ -664,11 +664,11 @@ static void armada_37xx_irq_handler(struct irq_desc *desc) u32 status; unsigned long flags; - spin_lock_irqsave(&info->irq_lock, flags); + raw_spin_lock_irqsave(&info->irq_lock, flags); status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); /* Manage only the interrupt that was enabled */ status &= readl_relaxed(info->base + IRQ_EN + 4 * i); - spin_unlock_irqrestore(&info->irq_lock, flags); + raw_spin_unlock_irqrestore(&info->irq_lock, flags); while (status) { u32 hwirq = ffs(status) - 1; u32 virq = irq_find_mapping(d, hwirq + @@ -695,12 +695,12 @@ static void armada_37xx_irq_handler(struct irq_desc *desc) update_status: /* Update status in case a new IRQ appears */ - spin_lock_irqsave(&info->irq_lock, flags); + raw_spin_lock_irqsave(&info->irq_lock, flags); status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); /* Manage only the interrupt that was enabled */ status &= readl_relaxed(info->base + IRQ_EN + 4 * i); - spin_unlock_irqrestore(&info->irq_lock, flags); + raw_spin_unlock_irqrestore(&info->irq_lock, flags); } } chained_irq_exit(chip, desc); @@ -731,7 +731,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, struct device *dev = &pdev->dev; unsigned int i, nr_irq_parent; - spin_lock_init(&info->irq_lock); + raw_spin_lock_init(&info->irq_lock); nr_irq_parent = of_irq_count(np); if (!nr_irq_parent) {