diff mbox series

[3/3] arm64/sysreg: Convert ID_AA64MMFR1_EL1 to automatic generation

Message ID 20220718112926.901844-4-kristina.martsenko@arm.com (mailing list archive)
State New, archived
Headers show
Series arm64/sysreg: Automatic generation of ID_AA64MMFR1_EL1 | expand

Commit Message

Kristina Martsenko July 18, 2022, 11:29 a.m. UTC 
Convert ID_AA64MMFR1_EL1 to be automatically generated as per DDI0487H.a,
no functional changes.

Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
---
 arch/arm64/include/asm/sysreg.h | 23 -----------
 arch/arm64/tools/sysreg         | 71 +++++++++++++++++++++++++++++++++
 2 files changed, 71 insertions(+), 23 deletions(-)

Comments

Mark Brown July 18, 2022, 12:02 p.m. UTC | #1 
On Mon, Jul 18, 2022 at 12:29:26PM +0100, Kristina Martsenko wrote:

> Convert ID_AA64MMFR1_EL1 to be automatically generated as per DDI0487H.a,
> no functional changes.

> +Sysreg	ID_AA64MMFR1_EL1	3	0	0	7	1
> +Enum	63:60	ECBHB
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum

This is RES0 in DDI0487H.a, but was already present upstream so it's
fine just not quite what the changelog said.

Reviewed-by: Mark Brown <broonie@kernel.org>
Kristina Martsenko July 18, 2022, 1:49 p.m. UTC | #2 
On 18/07/2022 13:02, Mark Brown wrote:
> On Mon, Jul 18, 2022 at 12:29:26PM +0100, Kristina Martsenko wrote:
> 
>> Convert ID_AA64MMFR1_EL1 to be automatically generated as per DDI0487H.a,
>> no functional changes.
> 
>> +Sysreg	ID_AA64MMFR1_EL1	3	0	0	7	1
>> +Enum	63:60	ECBHB
>> +	0b0000	NI
>> +	0b0001	IMP
>> +EndEnum
> 
> This is RES0 in DDI0487H.a, but was already present upstream so it's
> fine just not quite what the changelog said.

Good point, I'll update the commit message if I need to send a new version.

Thanks,
Kristina
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index be76b329c0bc..6f66f2189e88 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -200,7 +200,6 @@ 
 #define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
 
 #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
-#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
 #define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
 
 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
@@ -762,28 +761,6 @@ 
 #define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_48
 #endif
 
-/* id_aa64mmfr1 */
-#define ID_AA64MMFR1_EL1_ECBHB_SHIFT		60
-#define ID_AA64MMFR1_EL1_TIDCP1_SHIFT		52
-#define ID_AA64MMFR1_EL1_HCX_SHIFT		40
-#define ID_AA64MMFR1_EL1_AFP_SHIFT		44
-#define ID_AA64MMFR1_EL1_ETS_SHIFT		36
-#define ID_AA64MMFR1_EL1_TWED_SHIFT		32
-#define ID_AA64MMFR1_EL1_XNX_SHIFT		28
-#define ID_AA64MMFR1_EL1_SpecSEI_SHIFT		24
-#define ID_AA64MMFR1_EL1_PAN_SHIFT		20
-#define ID_AA64MMFR1_EL1_LO_SHIFT		16
-#define ID_AA64MMFR1_EL1_HPDS_SHIFT		12
-#define ID_AA64MMFR1_EL1_VH_SHIFT		8
-#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT		4
-#define ID_AA64MMFR1_EL1_HAFDBS_SHIFT		0
-
-#define ID_AA64MMFR1_EL1_VMIDBits_8		0
-#define ID_AA64MMFR1_EL1_VMIDBits_16		2
-
-#define ID_AA64MMFR1_EL1_TIDCP1_NI		0
-#define ID_AA64MMFR1_EL1_TIDCP1_IMP		1
-
 /* id_aa64mmfr2 */
 #define ID_AA64MMFR2_E0PD_SHIFT		60
 #define ID_AA64MMFR2_EVT_SHIFT		56
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 1ffde974d766..24cf02daaa6a 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -358,6 +358,77 @@  Enum	3:0	WFxT
 EndEnum
 EndSysreg
 
+Sysreg	ID_AA64MMFR1_EL1	3	0	0	7	1
+Enum	63:60	ECBHB
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	59:56	CMOW
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	55:52	TIDCP1
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	51:48	nTLBPA
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	47:44	AFP
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	43:40	HCX
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	39:36	ETS
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	35:32	TWED
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	31:28	XNX
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	27:24	SpecSEI
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	23:20	PAN
+	0b0000	NI
+	0b0001	IMP
+	0b0010	PAN2
+	0b0011	PAN3
+EndEnum
+Enum	19:16	LO
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	15:12	HPDS
+	0b0000	NI
+	0b0001	IMP
+	0b0010	HPDS2
+EndEnum
+Enum	11:8	VH
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	7:4	VMIDBits
+	0b0000	8
+	0b0010	16
+EndEnum
+Enum	3:0	HAFDBS
+	0b0000	NI
+	0b0001	AF
+	0b0010	DBM
+EndEnum
+EndSysreg
+
 Sysreg	SCTLR_EL1	3	0	1	0	0
 Field	63	TIDCP
 Field	62	SPINMASK