| Message ID | 20220719093316.37253-1-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: mediatek: mt8195-infra_ao: Set pwrmcu clocks as critical | expand |
On 19/07/2022 11:33, AngeloGioacchino Del Regno wrote: > The pwrmcu is responsible for power management and idle states in SSPM: > on older SoCs this was managed in Linux drivers like sspm/mcupm/eemgpu > but, at least on MT8195, this functionality was transferred to the ATF > firmware. > For this reason, turning off the pwrmcu related clocks from the kernel > will lead to unability to resume the platform after suspend and other > currently unknown PM related side-effects. > > Set the PWRMCU and PWRMCU_BUS_H clocks as critical to prevent the > kernel from turning them off, fixing the aforementioned issue. > > Fixes: e2edf59dec0b ("clk: mediatek: Add MT8195 infrastructure clock support") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/clk/mediatek/clk-mt8195-infra_ao.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c > index ce7ac16a2f42..75b54ec9c46c 100644 > --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c > +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c > @@ -55,8 +55,12 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { > #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ > GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0) > > +#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ > + GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \ > + &mtk_clk_gate_ops_setclr, _flag) > + > #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ > - GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) > + GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0) > > #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \ > GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \ > @@ -136,8 +140,11 @@ static const struct mtk_gate infra_ao_clks[] = { > GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_SYS, "infra_ao_unipro_sys", "top_ufs", 11), > GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_TICK, "infra_ao_unipro_tick", "top_ufs_tick1us", 12), > GATE_INFRA_AO2(CLK_INFRA_AO_UFS_MP_SAP_B, "infra_ao_ufs_mp_sap_b", "top_ufs_mp_sap_cfg", 13), > - GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU, "infra_ao_pwrmcu", "top_pwrmcu", 15), > - GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU_BUS_H, "infra_ao_pwrmcu_bus_h", "top_axi", 17), > + /* pwrmcu is used by ATF for platform PM: clocks must never be disabled by the kernel */ > + GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_PWRMCU, "infra_ao_pwrmcu", "top_pwrmcu", 15, > + CLK_IS_CRITICAL), > + GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_PWRMCU_BUS_H, "infra_ao_pwrmcu_bus_h", "top_axi", 17, > + CLK_IS_CRITICAL), > GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_B, "infra_ao_apdma_b", "top_axi", 18), > GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25), > GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
Quoting AngeloGioacchino Del Regno (2022-07-19 02:33:16) > The pwrmcu is responsible for power management and idle states in SSPM: > on older SoCs this was managed in Linux drivers like sspm/mcupm/eemgpu > but, at least on MT8195, this functionality was transferred to the ATF > firmware. > For this reason, turning off the pwrmcu related clocks from the kernel > will lead to unability to resume the platform after suspend and other > currently unknown PM related side-effects. > > Set the PWRMCU and PWRMCU_BUS_H clocks as critical to prevent the > kernel from turning them off, fixing the aforementioned issue. > > Fixes: e2edf59dec0b ("clk: mediatek: Add MT8195 infrastructure clock support") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- Applied to clk-next
diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index ce7ac16a2f42..75b54ec9c46c 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -55,8 +55,12 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0) +#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flag) + #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0) #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \ GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \ @@ -136,8 +140,11 @@ static const struct mtk_gate infra_ao_clks[] = { GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_SYS, "infra_ao_unipro_sys", "top_ufs", 11), GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_TICK, "infra_ao_unipro_tick", "top_ufs_tick1us", 12), GATE_INFRA_AO2(CLK_INFRA_AO_UFS_MP_SAP_B, "infra_ao_ufs_mp_sap_b", "top_ufs_mp_sap_cfg", 13), - GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU, "infra_ao_pwrmcu", "top_pwrmcu", 15), - GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU_BUS_H, "infra_ao_pwrmcu_bus_h", "top_axi", 17), + /* pwrmcu is used by ATF for platform PM: clocks must never be disabled by the kernel */ + GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_PWRMCU, "infra_ao_pwrmcu", "top_pwrmcu", 15, + CLK_IS_CRITICAL), + GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_PWRMCU_BUS_H, "infra_ao_pwrmcu_bus_h", "top_axi", 17, + CLK_IS_CRITICAL), GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_B, "infra_ao_apdma_b", "top_axi", 18), GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25), GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
The pwrmcu is responsible for power management and idle states in SSPM: on older SoCs this was managed in Linux drivers like sspm/mcupm/eemgpu but, at least on MT8195, this functionality was transferred to the ATF firmware. For this reason, turning off the pwrmcu related clocks from the kernel will lead to unability to resume the platform after suspend and other currently unknown PM related side-effects. Set the PWRMCU and PWRMCU_BUS_H clocks as critical to prevent the kernel from turning them off, fixing the aforementioned issue. Fixes: e2edf59dec0b ("clk: mediatek: Add MT8195 infrastructure clock support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/clk/mediatek/clk-mt8195-infra_ao.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)