@@ -149,6 +149,14 @@ &i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
+
+ cr50@50 {
+ compatible = "google,cr50";
+ reg = <0x50>;
+ interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cr50_int>;
+ };
};
&i2c4 {
@@ -426,6 +434,21 @@ &pio {
"AP_SPI_FLASH_MOSI",
"AP_SPI_FLASH_MISO";
+ cr50_int: cr50-irq-default-pins {
+ pins-gsc-ap-int-odl {
+ pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
+ input-enable;
+ };
+ };
+
+ cros_ec_int: cros-ec-irq-default-pins {
+ pins-ec-ap-int-odl {
+ pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ input-enable;
+ };
+ };
+
i2c0_pins: i2c0-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
@@ -669,6 +692,11 @@ &scp {
memory-region = <&scp_mem>;
pinctrl-names = "default";
pinctrl-0 = <&scp_pins>;
+
+ cros-ec-rpmsg {
+ compatible = "google,cros-ec-rpmsg";
+ mediatek,rpmsg-name = "cros-ec-rpmsg";
+ };
};
&spi0 {
@@ -677,6 +705,68 @@ &spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
mediatek,pad-select = <0>;
+
+ cros_ec: ec@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "google,cros-ec-spi";
+ reg = <0>;
+ interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cros_ec_int>;
+ spi-max-frequency = <3000000>;
+
+ cros_ec_pwm: ec-pwm {
+ compatible = "google,cros-ec-pwm";
+ #pwm-cells = <1>;
+ };
+
+ i2c_tunnel: i2c-tunnel {
+ compatible = "google,cros-ec-i2c-tunnel";
+ google,remote-bus = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mt_pmic_vmc_ldo_reg: regulator@0 {
+ compatible = "google,cros-ec-regulator";
+ reg = <0>;
+ regulator-name = "mt_pmic_vmc_ldo";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ mt_pmic_vmch_ldo_reg: regulator@1 {
+ compatible = "google,cros-ec-regulator";
+ reg = <1>;
+ regulator-name = "mt_pmic_vmch_ldo";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ typec {
+ compatible = "google,cros-ec-typec";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_c0: connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "host";
+ try-power-role = "source";
+ };
+
+ usb_c1: connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ power-role = "dual";
+ data-role = "host";
+ try-power-role = "source";
+ };
+ };
+ };
};
&u3phy0 {
@@ -728,3 +818,6 @@ &xhci3 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};
+
+#include <arm/cros-ec-keyboard.dtsi>
+#include <arm/cros-ec-sbs.dtsi>
Wire up the ChromeOS Embedded Controller on SPI0 and its communication channel via SCP RPMSG along with all of the offered functionality, including Keyboard, Smart Battery Metrics (SBS), PWM controller, I2C tunnel, regulators and Type-C connector management. While at it, also add support for the Cr50 Google Security Chip (GSC) found on this platform on I2C3 to support TPM and also use it as an entropy source for the kernel. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+)