| Message ID | 20220723235248.338837-1-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mp: Adjust PHY IRQ mode on i.MX8M Plus DHCOM PDK2 | expand |
> Subject: [PATCH] arm64: dts: imx8mp: Adjust PHY IRQ mode on i.MX8M Plus > DHCOM PDK2 > > Set SION bit and clear ODE and DSE bits for PHY IRQ IOMUXC settings. > The SION bit is needed to pass pin state into the SoC, the later are not > needed as this is an input pin. As I recall, only I2C needs set SION. Have you configure the GPIO as input? Regards Peng. > > Fixes: 8d6712695bc8e ("arm64: dts: imx8mp: Add support for DH electronics > i.MX8M Plus DHCOM and PDK2") > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Fabio Estevam <festevam@denx.de> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Shawn Guo <shawnguo@kernel.org> > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi > b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi > index d0839b10a4f2b..4262df2905a8d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi > @@ -793,7 +793,7 @@ pinctrl_ethphy1: dhcom-ethphy1-grp { > /* ENET1_#RST Reset */ > MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 > 0x11 > /* ENET1_#INT Interrupt */ > - MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 > 0x11 > + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 > 0x40000000 > >; > }; > > -- > 2.35.1
On 7/24/22 15:00, Peng Fan wrote: >> Subject: [PATCH] arm64: dts: imx8mp: Adjust PHY IRQ mode on i.MX8M Plus >> DHCOM PDK2 >> >> Set SION bit and clear ODE and DSE bits for PHY IRQ IOMUXC settings. >> The SION bit is needed to pass pin state into the SoC, the later are not >> needed as this is an input pin. > > As I recall, only I2C needs set SION. Have you configure the GPIO as input? You're right, I think these two are the right fix for this problem: https://lore.kernel.org/linux-gpio/20220724171057.18549-1-marex@denx.de/ https://lore.kernel.org/linux-gpio/20220724171057.18549-1-marex@denx.de/ Please drop this patch.
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index d0839b10a4f2b..4262df2905a8d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -793,7 +793,7 @@ pinctrl_ethphy1: dhcom-ethphy1-grp { /* ENET1_#RST Reset */ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11 /* ENET1_#INT Interrupt */ - MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40000000 >; };
Set SION bit and clear ODE and DSE bits for PHY IRQ IOMUXC settings. The SION bit is needed to pass pin state into the SoC, the later are not needed as this is an input pin. Fixes: 8d6712695bc8e ("arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK2") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> To: linux-arm-kernel@lists.infradead.org --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)