From patchwork Mon Jul 25 10:11:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12927940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AE5FC43334 for ; Mon, 25 Jul 2022 10:10:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4gSwih/dtJZPS7CIdhgdRaj9mHuydCgM4GpPqvLi1Vw=; b=v9bd4Z28oOMbYq LAJvvhfJV1GGiKZzVJSXq+s0mLWogni6F8NNZ91nQ1nJrQv/HVxSoJdphAtyMpviJvY2cm2bnuk3z WSQeFCHGH4zeMyfQYuHtmtz3Wybq1u371+m/PMYfXSGs2j0ZXGuPBgKu+D/I8amo7N4wbloVfZ+a1 wPs+bgJavRfKpOaiz+LB/zt3RcD7vGUVOhtk8W2cn8zn9r97Seb1X7HehhJUnSnaaybjUgqXsuYDL aUwLFY6W3q/Dlw3ZivytFyXe6ZpOIvU1u3avHJAE5hr4zLLoJAFtjf/LaxOPSLALxjWuvJcfwp4Yk Yk3v5MKHMOQ9hPAWdb6Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oFv1t-007yYw-A8; Mon, 25 Jul 2022 10:09:37 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oFv1T-007yIF-12 for linux-arm-kernel@lists.infradead.org; Mon, 25 Jul 2022 10:09:12 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1658743750; x=1690279750; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pfFlYQJ46XkjUNiMAdcxTdm9mH/GEjmoBFYjs3nO3f0=; b=cqZHSagtBDwV69+Cow8h10I/oQUiKTGrO3dyQ18GsFTO2bHUtMc8o8um eyQ4FhhHV+k3CwZ70oAb3hiz7cZyiV3A4x9byJ7s5CkGMnXh18/DmLCnL Ly/FtutIw+xjWm30z/fN/TkC64wcnjrpgAQSgwxvh5aEGrNcR/3vTg0xZ aUcw9anCCWIyghGDMH+RkQOIUYZ0S1Jpe/2NXFyPQipDsS1Q1Z112Sbq2 FW5EHtUJF+9e9hmKf5MFY3x2Y27+KCgu1S1ARFIQXMo/PdBFx1x6qBJVs uLECBbLOTRecta3p2XvZcsrNI5plQY00EZKtdRGbVzctlZxX3JI/Eoz2M A==; X-IronPort-AV: E=Sophos;i="5.93,192,1654585200"; d="scan'208";a="173666576" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Jul 2022 03:09:09 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 25 Jul 2022 03:09:09 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 25 Jul 2022 03:09:06 -0700 From: Claudiu Beznea To: , , , , , CC: , , , Claudiu Beznea Subject: [PATCH 1/5] ASoC: mchp-spdifrx: disable end of block interrupt on failures Date: Mon, 25 Jul 2022 13:11:26 +0300 Message-ID: <20220725101130.1780393-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220725101130.1780393-1-claudiu.beznea@microchip.com> References: <20220725101130.1780393-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220725_030911_099533_4289372B X-CRM114-Status: GOOD ( 11.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Disable end of block interrupt in case of wait for completion timeout or errors to undo previously enable operation (done in mchp_spdifrx_isr_blockend_en()). Otherwise we can end up with an unbalanced reference counter for this interrupt. Fixes: ef265c55c1ac ("ASoC: mchp-spdifrx: add driver for SPDIF RX") Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-spdifrx.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/sound/soc/atmel/mchp-spdifrx.c b/sound/soc/atmel/mchp-spdifrx.c index 0d37b78b94a0..b6a753893d90 100644 --- a/sound/soc/atmel/mchp-spdifrx.c +++ b/sound/soc/atmel/mchp-spdifrx.c @@ -288,15 +288,17 @@ static void mchp_spdifrx_isr_blockend_en(struct mchp_spdifrx_dev *dev) spin_unlock_irqrestore(&dev->blockend_lock, flags); } -/* called from atomic context only */ +/* called from atomic/non-atomic context */ static void mchp_spdifrx_isr_blockend_dis(struct mchp_spdifrx_dev *dev) { - spin_lock(&dev->blockend_lock); + unsigned int flags; + + spin_lock_irqsave(&dev->blockend_lock); dev->blockend_refcount--; /* don't enable BLOCKEND interrupt if it's already enabled */ if (dev->blockend_refcount == 0) regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND); - spin_unlock(&dev->blockend_lock); + spin_unlock_irqrestore(&dev->blockend_lock); } static irqreturn_t mchp_spdif_interrupt(int irq, void *dev_id) @@ -575,6 +577,7 @@ static int mchp_spdifrx_subcode_ch_get(struct mchp_spdifrx_dev *dev, if (ret <= 0) { dev_dbg(dev->dev, "user data for channel %d timeout\n", channel); + mchp_spdifrx_isr_blockend_dis(dev); return ret; }