diff mbox series

[1/2] arm64: dts: microchip: sparx5: remove PSCI

Message ID 20220725131521.607904-1-robert.marko@sartura.hr (mailing list archive)
State New, archived
Headers show
Series [1/2] arm64: dts: microchip: sparx5: remove PSCI | expand

Commit Message

Robert Marko July 25, 2022, 1:15 p.m. UTC 
PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot
that is shipped does not implement it as well.

I have tried flashing the latest vendor BSP U-boot which did not work.
After contacting Microchip, they confirmed that there is no ATF for the
SoC nor PSCI implementation which is unfortunate in 2022.

So, disable PSCI as otherwise kernel crashes as soon as it tries probing
PSCI with, and the crash is only visible if earlycon is used.

Tested on PCB134 with eMMC (VSC5640EV).

Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
 arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 -----
 1 file changed, 5 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 2dd5e38820b1..38da24c1796c 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -61,11 +61,6 @@  arm-pmu {
 		interrupt-affinity = <&cpu0>, <&cpu1>;
 	};
 
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,