| Message ID | 20220725131521.607904-2-robert.marko@sartura.hr (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] arm64: dts: microchip: sparx5: remove PSCI | expand |
On Mon, Jul 25, 2022 at 3:15 PM Robert Marko <robert.marko@sartura.hr> wrote: > > As described in previous commit, PSCI is not implemented on this SoC at > all, so use spin-tables to bringup the cores. > > Tested on PCB134 with eMMC (VSC5640EV). > > Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") > Signed-off-by: Robert Marko <robert.marko@sartura.hr> > --- Surely this is only a machine specific bug in the boot loader, not something the SoC is incapable of supporting, right? > arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi > index 38da24c1796c..ea2b07ca2887 100644 > --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi > +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi > @@ -40,14 +40,16 @@ cpu0: cpu@0 { > compatible = "arm,cortex-a53"; > device_type = "cpu"; > reg = <0x0 0x0>; > - enable-method = "psci"; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x0000fff8>; > next-level-cache = <&L2_0>; > }; I think the psci method should be kept in the dtsi file here, since actual product boards would have to support it to be useful, you can just add the spin-table as an override in the broken reference boards, with a comment about which u-boot version is broken, in case this gets fixed in the future. Arnd
On Mon, Jul 25, 2022 at 3:33 PM Arnd Bergmann <arnd@arndb.de> wrote: > > On Mon, Jul 25, 2022 at 3:15 PM Robert Marko <robert.marko@sartura.hr> wrote: > > > > As described in previous commit, PSCI is not implemented on this SoC at > > all, so use spin-tables to bringup the cores. > > > > Tested on PCB134 with eMMC (VSC5640EV). > > > > Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") > > Signed-off-by: Robert Marko <robert.marko@sartura.hr> > > --- > > Surely this is only a machine specific bug in the boot loader, not something > the SoC is incapable of supporting, right? PSCI itself could be implemented on this SoC, you can even implement it just by using U-boot. I have been looking into adding basic reset and core bring up PSCI support to the BSP U-boot for start. > > > > arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++++-- > > 1 file changed, 4 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi > > index 38da24c1796c..ea2b07ca2887 100644 > > --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi > > +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi > > @@ -40,14 +40,16 @@ cpu0: cpu@0 { > > compatible = "arm,cortex-a53"; > > device_type = "cpu"; > > reg = <0x0 0x0>; > > - enable-method = "psci"; > > + enable-method = "spin-table"; > > + cpu-release-addr = <0x0 0x0000fff8>; > > next-level-cache = <&L2_0>; > > }; > > I think the psci method should be kept in the dtsi file here, since actual > product boards would have to support it to be useful, you can just add > the spin-table as an override in the broken reference boards, with a > comment about which u-boot version is broken, in case this gets fixed > in the future. Well, that's the thing, Microchip-s BSP is not utilizing PSCI at all, they reverted to using spin-tables in both Linux and U-boot, and they dont implement PSCI at all. I highly doubt that any of the vendors are gonna implement it themselves. I have contacted Microchip and they confirmed that there is no PSCI support, they stated that they started working on PSCI but that images were larger and took longer to boot and they dont see any advantage so they removed that. So I doubt that we are gonna be seeing any boards that implement PSCI by default. I can tell you that it's annoying me as we are back to 2013 and using a GPIO for restart. U-boot version that I tested is the last one from their 2022.06 BSP, its based off U-boot 2019.10. Maybe somebody from Microchip can chime in on this? Regards, Robert > > > Arnd
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 38da24c1796c..ea2b07ca2887 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -40,14 +40,16 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x0>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x1>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; next-level-cache = <&L2_0>; }; L2_0: l2-cache0 {
As described in previous commit, PSCI is not implemented on this SoC at all, so use spin-tables to bringup the cores. Tested on PCB134 with eMMC (VSC5640EV). Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)