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[88.207.96.123]) by smtp.googlemail.com with ESMTPSA id h14-20020aa7de0e000000b0043a7404314csm7124969edv.8.2022.07.25.06.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 06:15:29 -0700 (PDT) From: Robert Marko To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lars.povlsen@microchip.com, Steen.Hegelund@microchip.com, UNGLinuxDriver@microchip.com, arnd@arndb.de, alexandre.belloni@bootlin.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 2/2] arm64: dts: microchip: sparx5: dont use PSCI for core bringup Date: Mon, 25 Jul 2022 15:15:21 +0200 Message-Id: <20220725131521.607904-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220725131521.607904-1-robert.marko@sartura.hr> References: <20220725131521.607904-1-robert.marko@sartura.hr> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220725_061533_382629_0F22A605 X-CRM114-Status: GOOD ( 12.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As described in previous commit, PSCI is not implemented on this SoC at all, so use spin-tables to bringup the cores. Tested on PCB134 with eMMC (VSC5640EV). Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 38da24c1796c..ea2b07ca2887 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -40,14 +40,16 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x0>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x1>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; next-level-cache = <&L2_0>; }; L2_0: l2-cache0 {