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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: l+F3/BnhQenHoxlGGFrMWmCJVmmysEzH8tstsjBrgQnResBfvPEqp24/vQSVokwXZLCtGI1B86UKLuu6NaiA9z6WqgLCmwqynU3+LFNtOJwg3lDXEANsvTNdmiUOosV2iLX9+xKlz/zI92B7/raRBisjFVwXA4BBPS72v5Jgt1Vonw/TVN8ZxjApA2hHxSfXD0p156D7q1ZyQhN1RmCr62+6K5BeEOYTQgkiRlidcLnvExGuvYo4ru5Je8mO0xkeXX9LVkix4DqrPwJsvq0xk3LBTl3Wj5O77YyLBR5i3REYhiDl5/OTnFIbZWRK74tcxoKKHBdbj7VvXOKtSTcPsAZA/4T8ipOp1gTYkDKvSOrBbwC+XjsQKYRoE9d8CBzqxLP9vuY2L90w2VwIHJoRhTy+he8+5aOQeTtEZanvXj01+8WWan1VdoQK3+EDcFMg2ZGAfESYhhj+IX2GTSph5IM1CVkU4AY4ZNl42y45kglg4JExuOWAP/tyJapOY8JehRBzq4xtxLbIwCF4vFGFMLSGwWnUaIDeami0PVQv8v9QDIeHdK4v9SaFW7t6910strUAwSS3/sMHGh2eYLvfSSbm2XoE2uIsC+G1rD0VCNH7e0ofiD/HavMS+sHdBK5OAdslLYQ4rGKMb466zTWO2poOpxr2SkeEATcD6X4WTHNjuzaVEtFu8IXyQn8aSymd2Z297g0NeaGgCeC7GdvdnYL+ZF9SShuzIMaYHQPWf3JOf941wP/9zBi9pgVhE4J1nHHWwMDVVqgUZiFNJs8Q6j2KRvSNd7j5RUNYVqcyhgwhnp6DR842cgtsXZNdVzpqBsmoP/8Ypiw6yT8+6QGfbuH+G2QyBgSGLYMtVu4JPI6KXtnOi02ckhzEJzh404zf7Q0hSuMfOZOuX9+VRL7L09+cZJUrLbW6xzCViQ004tVdGoG0465BmCwU9GSh+efm/65qGz0q2IqeL7jNEe+Cn+qM5+ybwgdA1mc8KghAz/a6aLDnT3PKCevokubqvrrXMnmHVM7RDGalIMLXNyHpoMMnm0i42M8jdROLDrTRM1ZYXB+NvZ7WLisd0cvt7T0W3izEmIpuHKlWRMBn08P8cvmup5VC6Pj5ariUTLJq2ethQbOcD+F96FKh61OLwwpn19RzRlzOnuoFMc187UEHqJ0wk0w3hXdBQqvLMclEv4L/e5cYm2AtJwb70Mvr+BmzkT2lWn/RJWwPSQbWexoVvXFQR6jh9dTDWbe6y9H9t+Lvkz62XGYTEW/l359K8aTw73/4rs/v4vgXnnvPC6DOAOF+QTOIYxeXNVWPzm//oyh57QX6U44sLWPD5gj+NlokGWlrDERWdMOgKwnYT7w3K9+aDtICi2ozd548zVL7IFu+0apro4RVV5KD/1pPkaqla/940YuLIMKrzhR0nM3GF14A34Qv8n112XnPTCuLz4+R8MO/kuTX3zBhoGz3XOd8M2AkPJTmLheWJdyIJ6MeWIDRUKB2tmNbtqt7i2Y7V0CqKGnYAia1y+46If7aVigo0NoHsMcvKWn78WmFQ9jiXySrnsNy2L5JLSe6cCqIyNNSC4TU5ujS0qxX6BhCkN9z X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a3b7a24b-38e2-4328-ad3f-08da74564d7f X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Aug 2022 07:12:04.4131 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4htUVKorwC9t7JlvjAN5jpDNdRDzLQ2uM6r1eKjrtlf6UTdaJpKTJsS2wNZAs6Om+7sc/sByXJvBQyHjK9srLQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6429 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220802_001212_634443_1148315B X-CRM114-Status: GOOD ( 18.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, like I2C controller, PWM controller, MIPI DSI controller and Control and Status Registers (CSR) module. Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel link MSI bus specific bindings. Signed-off-by: Liu Ying --- .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml new file mode 100644 index 000000000000..24f50535f5c2 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus + +maintainers: + - Liu Ying + +description: | + i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os + sitting together with the PHYs. It is not the same as the MSI bus coming + from i.MX8 System Controller Unit (SCU) which is used to control power, + clock and reset through the i.MX8 Distributed Slave System Controller (DSC). + + i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks, + that is, MSI clock and AHB clock, need to be enabled so that peripherals + connected to the bus can be accessed. Also, the bus is part of a power + domain. The power domain needs to be enabled before the peripherals can + be accessed. + + Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, + like I2C controller, PWM controller, MIPI DSI controller and Control and + Status Registers (CSR) module, are accessed through the bus. + + The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp + pixel link MSI bus controller and does not allow SCFW user to control it. + So, the controller's registers cannot be accessed by SCFW user. Hence, + the interrupts generated by the controller don't make any sense from SCFW + user's point of view. + +allOf: + - $ref: simple-pm-bus.yaml# + +properties: + compatible: + items: + - enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + - {} # simple-pm-bus, but not listed here to avoid false select + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: master gated clock from system + - description: AHB clock + + clock-names: + items: + - const: msi + - const: ahb + +required: + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + bus@56200000 { + compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x56200000 0x20000>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <320>; + ranges; + clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>, + <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>; + clock-names = "msi", "ahb"; + power-domains = <&pd IMX_SC_R_DC_0>; + };