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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nSKcYp1lOiDcpcvOt2SALyMum/EmPFB7ucq4ZEdr3TgUVpfC7FIdHsbb5gy9leEWRJISKlsDlEQw3o1AfLm3y9f6VcMg57K+AFWyWptVm+QsLIRdSjxgFcFwNcSmWfRbbHbhkbKI0Uzn7ofbkpU2lttpXXPkxfd/3ki6KtdF898wbJ/ysHTHjxGo+99MEef2j+YLbIWCrPxCZ9BaMTUgPCAXbU2zagmFdkN+mrH7tB5UbKIkfUYzqsGhh5Zq9SQBjduWdOGhen/LPEfO2clTw1KHnlthmMKzYG55fcBVoRhEVgB9ehA8wl9wxceFP0JASSvhModC8GynjbSx8kxBTREGaldmmJ40Rfw6u8ToXmVHKn1UN5VuWIpMamaloWHG/fHk0RYK6QTyAdupBo+BLBkoTIpXYnc2GWTkhqd3fWadszDW0TX0MNvEzHFlr6zRss3x4zCp1ZWOBL9LitkaqX2hFQYyyReBwkGz3+XELKa8PWse9Xu1io6Gi2CGk1YATiuohWPXFssueS2xj7n97dx/cSgNyDEpL38K46ZsHnvketNWUGkjLWZ3ZyIxklf1K1/7IYWgta+hZ85EF8l2Tso/ddPBRVOfVGXwWnStGlFCeNe2EnP3GnZDn8aw5sWqeWok2lqg2bQ5kKJM9vd4pab106h6U+kaOZIOIgMvJActO6HThtAafo51aUGv1SfWxeayaXnb5+wxMpWViXNVYIT7v3SF+OHu1OIur7R4QhpLxjSo8N1WO359YY5MTsOSr5P5hzmC4gwgtQlHcij0W4dL6x2hBjbEB2Ec24YP1Ux94e9MOOLOV3nYTioAplUy5ayyBilxVcFC+BrKwwKnCOfJ5JYknQfQ0bvZECDP71jjECIHMC/uKE8d8+5O9qw5i08SWyl09ciy9EKyzhK025hLFmV0Fbm5Uz5pq2Rg2OwhZ/vcwpZt0OaWx2x6YokL2Sh3H3fIf3ZI0zEDaAZ2aFRXwISYvk9/fJhxKh8kmDYX2oEHgVOJWDD0BhxKAgeQjRf4kUvTndKpNIfKGbTgDMWzllcuPV0R56/iME+Aa51R5AjJAb+PlSQX61V4B1iZaj9tYo4Ktbga1l/NH+aNrLn2n9vkYbVDmgZ1pAIy6CdNzs7zdGPRQ0XPnFMd3PiGjc0omI9caGD8VVmxLDXY9XEuKtSnmthTSvJ0lfC+scmo45HiQrXmr+QZj8d/SGFr8WzjsgHuyDJOLShxlizKsJLBChOqxrVcSk50Hti4p5F6r6Srbww2bBqGGvDGDTUMLu9iUBz1XjqZ1U3shgMVsy0IA0WEiUBQP1UnIEX48Akwn7pa5KCla4wHB2cM07Da/Q5lHZTXLRfIVNpKz6KkBtaGw6domEfLQp8f7P3RbT5tkZkdUpxuJhO89HZXQWzBF04yve2ZWKIGVVY5VMKsf8xoqme5s6fqxmRikRiwESqw2WqSFVY9d9mROmbs9JIAroJn8ME9+L9MwGRD6j08N9ObSIymyjhG9htIUVO9OeIsUCxXQaChvFgAn0Q9AXEzm4NCLlV5eTqX+wySq7EFtbMUD96Nj6qu0F5ZWBTN/zCWYkOyrDV2ieLPUAtMYztt X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7659afe3-4880-40f6-8393-08da74eeb26a X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2022 01:22:57.3198 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VDplbtHiB4bE7TMCP8zwys3roe5vlOtVX78/fQHWtAwVQ4pKByI9joHoTPdlZTHX3nzuWgjbKV0dVTVmmivBJw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6891 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220802_182259_748050_A42462E2 X-CRM114-Status: GOOD ( 18.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, like I2C controller, PWM controller, MIPI DSI controller and Control and Status Registers (CSR) module. Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel link MSI bus specific bindings. Signed-off-by: Liu Ying --- v1->v2: Address Krzysztof's comments: * Add a select to explicitly select the MSI bus dt-binding. * List 'simple-pm-bus' explicitly as one item of compatible strings. * Require compatible and reg properties. * Put reg property just after compatible property in example. .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml new file mode 100644 index 000000000000..358c032041e5 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus + +maintainers: + - Liu Ying + +description: | + i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os + sitting together with the PHYs. It is not the same as the MSI bus coming + from i.MX8 System Controller Unit (SCU) which is used to control power, + clock and reset through the i.MX8 Distributed Slave System Controller (DSC). + + i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks, + that is, MSI clock and AHB clock, need to be enabled so that peripherals + connected to the bus can be accessed. Also, the bus is part of a power + domain. The power domain needs to be enabled before the peripherals can + be accessed. + + Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, + like I2C controller, PWM controller, MIPI DSI controller and Control and + Status Registers (CSR) module, are accessed through the bus. + + The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp + pixel link MSI bus controller and does not allow SCFW user to control it. + So, the controller's registers cannot be accessed by SCFW user. Hence, + the interrupts generated by the controller don't make any sense from SCFW + user's point of view. + +allOf: + - $ref: simple-pm-bus.yaml# + +# We need a select here so we don't match all nodes with 'simple-pm-bus'. +select: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + required: + - compatible + +properties: + compatible: + items: + - enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + - const: simple-pm-bus + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: master gated clock from system + - description: AHB clock + + clock-names: + items: + - const: msi + - const: ahb + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + bus@56200000 { + compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus"; + reg = <0x56200000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <320>; + ranges; + clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>, + <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>; + clock-names = "msi", "ahb"; + power-domains = <&pd IMX_SC_R_DC_0>; + };