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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QcU5sBxYDJqIIiiaJqzj2PpwAtUrr9dyLqZ7wne7phjUUbRcFLSJ7pfuov4ID91A4MNmKVrbkgGY8C+/1PFQ3IaLLP2Z603KNwCOpux0qHVjFEPK3a4oIPoczJU+k2H1glRqAAcWLyUxpAzHUdtHbfBpdVXB8naOq2mz8Shtt1KiZIcvuC403POfSGlgKsK0FF6Q2Y4lY3CJ/IMQumoat3on3YwDWwn0cuXxDQMZAmdoISx9pVlzoPxP7iBPlrgGHoc+2KVQ1cVw+7rPsWuCZ97kzUzyrT5z5SvhBRYEmWku7BVERLpIn6vffT/n16sxdTt0uXySYbJshfUQmxZSIo8ABqbSmzoj17Ds3F7TCz7+4V4PELfOupa+hW1Gn5pvmVzwXdzgbu2U1c3U4by4DR3Fq3aMkQgWiHHzrm8JSUj+igVex47KLDyA6hp9ZpaPrhfp3VDZECXdP9T+NOdk+Ervb7exwSomqSq7nRFmOM4nJjdKRVzKxxt8RaKz9hXYGggIIcPMLLGCobYnWeMR8bwQlP1wK2aI9Cyuf79A0QkhBq+3yS+Ppr9W/scI+BnytSBofhWNUK+LswEPE1JiUwTiA85KuFAo1INjIVhNkR3hNT6cABT8unQ89a2WKH7mxiF47t1dz3nEuIJxuMNrtBIwUMPoZ7zUZ2Ct3wsg/sBVokJdwMPxfzQ6z3B0n3zgJHrqFlwpq5JervNb1y7G9S7TQ/UuaXO3isjB10d5e2PXsj4gvro3qe0TwD2diEjOo9PK+IC90p1IXRPkTI63jU0uERf5DZDvQwMVu6kzraOZZOO5okaILKbmW8T2snATYjBZa+ZWuTMpwlT3kkR01GXAKUf+PhQNP+4YKqpX9BQhVWrsCUsU/eOUYNhHRzxKeXy2kKCgk98ohFwbrMAmuVwW1kHrklf1XB+yQ6KjpMAxNqMFpyrVaaHrvUFCEsgK1QPTEM8Im8JWgeuqHp5QQ8pYeSTGzGRo/d32ViCKSDrGuxr274vO1kaJaw0S9QIpDXA7Ytk4rWqalxtXh0NzWiVE0aT4HOh9euNwDA9rQhsjipTe+2UJAzh9w0XpAqt2RJfIWc0pKQykdugJ7/QTYelugJurtjjV9RxENBIdgvoVr7+9byKHoaWQVncO11RcGaOdHTYUSP+K9eW8ozJC05L8seKdI47B1dcZRYJvKno4ecbZLHMm2Q1SPBtHPa0ZrkILv94m8UaZZn2JRUmeAwHReLCgANCWmHc+r60Mm+If7OWgaqhPQkwhrRoGbmxmuHPtOa1lyNID+1sDhOi5Srqdzsj5ZP9WGS4SVhk2Esrx3XC0M0+Cl3X96omM0BRugKxadZ+Hftg99MUZPbcRx8TUlfvGGAqOAx3y26Px8EQBfgvz9lOS1crymGLvHsoOJfVvL8jIuQKJdP4dc2yz0TWFjmbAKqZCkZ6Us19X9zccLSlpHWSblyr17jXEZZh4k5n0WisSfJl3D2OMxvZljAKPSJxIeGlJHE81bGOkJW1DG9r7BI0TgM6g9qeb00pxmZjLHlg6DlHcKnmdMoTB4/2iyxI0DjzA8t6bOfzTUwAQ8fAJHFDWkyVgEnKIOlzpahBDBj75e+lYiLoIbyzing== X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-Network-Message-Id: a8e19e34-415d-4222-b6ff-08da76659351 X-MS-Exchange-CrossTenant-AuthSource: DB7PR03MB4972.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2022 22:06:26.2508 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: unOBdQccy9sXbnrEE2wqPQ6UtCa8RdpQZRJQtmmFlNxjprEQt22JF483nGSu1VEyU4PcZVxykHtkomJjueAgaQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB8419 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220804_150637_141240_FA886C8C X-CRM114-Status: GOOD ( 15.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds appropriate bindings for the macs which use the SerDes. The 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is no driver for this device (and as far as I know all you can do with the 100MHz clocks is gate them), so I have chosen to model it as a single fixed clock. Note: the SerDes1 lane numbering for the LS1046A is *reversed*. This means that Lane A (what the driver thinks is lane 0) uses pins SD1_TX3_P/N. Because this will break ethernet if the serdes is not enabled, enable the serdes driver by default on Layerscape. Signed-off-by: Sean Anderson --- This depends on [1]. [1] https://lore.kernel.org/netdev/20220804194705.459670-4-sean.anderson@seco.com/ Changes in v4: - Convert to new bindings .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 112 ++++++++++++++++++ drivers/phy/freescale/Kconfig | 1 + 2 files changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 7025aad8ae89..a848556bd7db 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -10,6 +10,8 @@ /dts-v1/; +#include + #include "fsl-ls1046a.dtsi" / { @@ -26,8 +28,110 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + clocks { + clk_100mhz: clock-100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk_156mhz: clock-156mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + }; }; +&serdes1 { + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; + status = "okay"; + + /* + * XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane numbers and pin + * numbers are _reversed_. In addition, the PCCR documentation is + * _inconsistent_ in its usage of these terms! + * + * PCCR "Lane 0" refers to... + * ==== ===================== + * 0 Lane A + * 2 Lane A + * 8 Lane A + * 9 Lane A + * B Lane D! + */ + serdes1_0: phy@0 { + #phy-cells = <0>; + reg = <0>; + + /* SGMII.6 */ + sgmii-0 { + fsl,pccr = <0x8>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_1: phy@1 { + #phy-cells = <0>; + reg = <1>; + + /* SGMII.5 */ + sgmii-1 { + fsl,pccr = <0x8>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_2: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* SGMII.10 */ + sgmii-2 { + fsl,pccr = <0x8>; + fsl,index = <2>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* XFI.10 */ + xfi-0 { + fsl,pccr = <0xb>; + fsl,index = <0>; + fsl,cfg = <0x2>; + fsl,type = ; + }; + }; + + serdes1_3: phy@3 { + #phy-cells = <0>; + reg = <3>; + + /* SGMII.9 */ + sgmii-3 { + fsl,pccr = <0x8>; + fsl,index = <3>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* XGI.9 */ + xfi-9 { + fsl,pccr = <0xb>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; +}; + + &duart0 { status = "okay"; }; @@ -140,21 +244,29 @@ ethernet@e6000 { ethernet@e8000 { phy-handle = <&sgmii_phy1>; phy-connection-type = "sgmii"; + phys = <&serdes1_1>; + phy-names = "serdes"; }; ethernet@ea000 { phy-handle = <&sgmii_phy2>; phy-connection-type = "sgmii"; + phys = <&serdes1_0>; + phy-names = "serdes"; }; ethernet@f0000 { /* 10GEC1 */ phy-handle = <&aqr106_phy>; phy-connection-type = "xgmii"; + phys = <&serdes1_3>; + phy-names = "serdes"; }; ethernet@f2000 { /* 10GEC2 */ fixed-link = <0 1 1000 0 0>; phy-connection-type = "xgmii"; + phys = <&serdes1_2>; + phy-names = "serdes"; }; mdio@fc000 { diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index fe2a3efe0ba4..9595666213d0 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -43,6 +43,7 @@ config PHY_FSL_LYNX_10G tristate "Freescale Layerscale Lynx 10G SerDes support" select GENERIC_PHY select REGMAP_MMIO + default y if ARCH_LAYERSCAPE help This adds support for the Lynx "SerDes" devices found on various QorIQ SoCs. There may be up to four SerDes devices on each SoC, and each