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Fri, 12 Aug 2022 15:25:39 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id f17-20020a05620a409100b006b942ae928bsm2788878qko.71.2022.08.12.15.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Aug 2022 15:25:37 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Rob Herring , Broadcom internal kernel review list , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH v5 1/3] dt-bindings: memory-controller: Document Broadcom STB MEMC Date: Fri, 12 Aug 2022 15:25:31 -0700 Message-Id: <20220812222533.2428033-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220812222533.2428033-1-f.fainelli@gmail.com> References: <20220812222533.2428033-1-f.fainelli@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220812_152553_345561_D1F619FB X-CRM114-Status: GOOD ( 16.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the Broadcom STB memory controller which is a trivial binding for now with a set of compatible strings and single register. Since we introduce this binding, the section in Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt is removed and this binding is referenced instead. Reviewed-by: Rob Herring Signed-off-by: Florian Fainelli --- .../bindings/arm/bcm/brcm,brcmstb.txt | 11 +--- .../brcm,brcmstb-memc-ddr.yaml | 52 +++++++++++++++++++ 2 files changed, 54 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index 104cc9b41df4..e797d2f69f3b 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -187,15 +187,8 @@ Required properties: Sequencer DRAM parameters and control registers. Used for Self-Refresh Power-Down (SRPD), among other things. -Required properties: -- compatible : should contain one of these - "brcm,brcmstb-memc-ddr-rev-b.2.1" - "brcm,brcmstb-memc-ddr-rev-b.2.2" - "brcm,brcmstb-memc-ddr-rev-b.2.3" - "brcm,brcmstb-memc-ddr-rev-b.3.0" - "brcm,brcmstb-memc-ddr-rev-b.3.1" - "brcm,brcmstb-memc-ddr" -- reg : the MEMC DDR register range +See Documentation/devicetree/bindings/memory-controllers/brcm,memc.yaml for a +full list of supported compatible strings and properties. Example: diff --git a/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml new file mode 100644 index 000000000000..4b072c879b02 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Memory controller (MEMC) for Broadcom STB + +maintainers: + - Florian Fainelli + +properties: + compatible: + items: + - enum: + - brcm,brcmstb-memc-ddr-rev-b.1.x + - brcm,brcmstb-memc-ddr-rev-b.2.0 + - brcm,brcmstb-memc-ddr-rev-b.2.1 + - brcm,brcmstb-memc-ddr-rev-b.2.2 + - brcm,brcmstb-memc-ddr-rev-b.2.3 + - brcm,brcmstb-memc-ddr-rev-b.2.5 + - brcm,brcmstb-memc-ddr-rev-b.2.6 + - brcm,brcmstb-memc-ddr-rev-b.2.7 + - brcm,brcmstb-memc-ddr-rev-b.2.8 + - brcm,brcmstb-memc-ddr-rev-b.3.0 + - brcm,brcmstb-memc-ddr-rev-b.3.1 + - brcm,brcmstb-memc-ddr-rev-c.1.0 + - brcm,brcmstb-memc-ddr-rev-c.1.1 + - brcm,brcmstb-memc-ddr-rev-c.1.2 + - brcm,brcmstb-memc-ddr-rev-c.1.3 + - brcm,brcmstb-memc-ddr-rev-c.1.4 + - const: brcm,brcmstb-memc-ddr + + reg: + maxItems: 1 + + clock-frequency: + description: DDR PHY frequency in Hz + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + memory-controller@9902000 { + compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr"; + reg = <0x9902000 0x600>; + clock-frequency = <2133000000>; + };