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Thu, 27 Oct 2022 08:53:14 -0400 (EDT) From: Maxime Ripard Date: Thu, 27 Oct 2022 14:52:47 +0200 Subject: [PATCH v5 7/7] drm/vc4: Make sure we don't end up with a core clock too high MIME-Version: 1.0 Message-Id: <20220815-rpi-fix-4k-60-v5-7-fe9e7ac8b111@cerno.tech> References: <20220815-rpi-fix-4k-60-v5-0-fe9e7ac8b111@cerno.tech> In-Reply-To: <20220815-rpi-fix-4k-60-v5-0-fe9e7ac8b111@cerno.tech> To: Stephen Boyd , Florian Fainelli , Maxime Ripard , Scott Branden , Broadcom internal kernel review list , Michael Turquette , Daniel Vetter , Emma Anholt , David Airlie , Ray Jui Cc: linux-rpi-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Stevenson , Maxime Ripard , dri-devel@lists.freedesktop.org, Dom Cobley , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Stefan Wahren X-Mailer: b4 0.11.0-dev-99e3a X-Developer-Signature: v=1; a=openpgp-sha256; l=2058; i=maxime@cerno.tech; h=from:subject:message-id; bh=idKX39IZNRr15VFsJbs3Y0d0YRgsqMO9SnCUIwEP+ZQ=; b=owGbwMvMwCX2+D1vfrpE4FHG02pJDMlR9TJ7I+L36tWeeVRUMNn3s30OT4VKV8aKTWI+x0V/eMr1 rfDuKGVhEONikBVTZIkRNl8Sd2rW6042vnkwc1iZQIYwcHEKwESU5BkZLr+VnFTzp+toilxleN2zj9 mRPN/6lx+Ms56zd6u6EVPnT0aGk1fEq5RKzj6+UGl/4lvbk7KOm8vufv12ZtPtZfx1JyxOMQAA X-Developer-Key: i=maxime@cerno.tech; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221027_055317_326245_66C72673 X-CRM114-Status: GOOD ( 10.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Following the clock rate range improvements to the clock framework, trying to set a disjoint range on a clock will now result in an error. Thus, we can't set a minimum rate higher than the maximum reported by the firmware, or clk_set_min_rate() will fail. Thus we need to clamp the rate we are about to ask for to the maximum rate possible on that clock. Reviewed-by: Dave Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_kms.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index 4419e810103d..5c97642ed66a 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -396,8 +396,8 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state) if (vc4->is_vc5) { unsigned long state_rate = max(old_hvs_state->core_clock_rate, new_hvs_state->core_clock_rate); - unsigned long core_rate = max_t(unsigned long, - 500000000, state_rate); + unsigned long core_rate = clamp_t(unsigned long, state_rate, + 500000000, hvs->max_core_rate); drm_dbg(dev, "Raising the core clock at %lu Hz\n", core_rate); @@ -431,14 +431,17 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state) drm_atomic_helper_cleanup_planes(dev, state); if (vc4->is_vc5) { - drm_dbg(dev, "Running the core clock at %lu Hz\n", - new_hvs_state->core_clock_rate); + unsigned long core_rate = min_t(unsigned long, + hvs->max_core_rate, + new_hvs_state->core_clock_rate); + + drm_dbg(dev, "Running the core clock at %lu Hz\n", core_rate); /* * Request a clock rate based on the current HVS * requirements. */ - WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate)); + WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); drm_dbg(dev, "Core clock actual rate: %lu Hz\n", clk_get_rate(hvs->core_clk));