From patchwork Mon Aug 15 16:26:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12943859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DF47C00140 for ; Mon, 15 Aug 2022 16:50:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5VMJTXuI6PgQhD2WgvK83cxrWuabZp0SdLEsron0rNo=; b=NX5PbN61c0KqDe EVP+25nmclaQZlRZAu5AovkJel9lGhwyFS3JttWUAVkFz1zoiskIk5G4ERom4LHABJKlp3/7JTo51 rJBD4K9lR2Um6JEKQNLIe/v83TVocrij/C7koAqiRURckJ45vqG8LHwLcm8C/eQiJsd6QVcgasr/l VKkAXeLUR+70BpEdnwJKPBgBHmvCUZ9bPW26ZEnYU6VrSLUHof4VBxFPforaiyN5/LLWfsqn5Er0L P5+iBOJ2ZKOSOHqiDOKbrvaJKrXfgDEE0FbC4R24SFwqeRfAyGPX4epuYHiXnv9O8bHCM9RupeMne 7INj6yiab34+F2zPXZxQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNdH6-001rsB-Ny; Mon, 15 Aug 2022 16:49:13 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNcw5-001cZD-Mp for linux-arm-kernel@lists.infradead.org; Mon, 15 Aug 2022 16:27:34 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 49B4F611BE; Mon, 15 Aug 2022 16:27:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7AD69C433D7; Mon, 15 Aug 2022 16:27:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660580847; bh=QEZL/GEyk0t+A3+qKTZsLdQtomfOOrQ0pXi1xphfeMM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GhcmBL00xEHaCbgVFs3KRyvev1FulSGT2xEO1yWoIZNpEp79yVPc0kRaAVZ/iu3FR QYH7pf2Gsq8XpY1XfAu9LXYa+BsQa/+mulOT5eEB0XXwemOayL4BN577aaBzlGaNRx 6Ys9d5U9OFQ6cX5wGQc7DgZXnL3hzn6fs43QBcsB2jsLTZNcBVGyilJbPHJsGp0uQu SHVh3mHxLa2MeVlV5F6/oxxyuiyZsuAZxjVa7/LXFd3Utt2mwIXSHx9J14E6bLgf7Z FRjjYyFf4qpEmSKatIZOrXaBnh+VK4tjw/KHGR5zmNHzijTSvGI9QjVRUZ1LxlJpWr hqBgWU8M2xoCw== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v2 09/28] arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.ASIDBits Date: Mon, 15 Aug 2022 17:26:29 +0100 Message-Id: <20220815162648.781802-10-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220815162648.781802-1-broonie@kernel.org> References: <20220815162648.781802-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3648; i=broonie@kernel.org; h=from:subject; bh=QEZL/GEyk0t+A3+qKTZsLdQtomfOOrQ0pXi1xphfeMM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBi+nO1LFrngA2jrZdKMrhBvLDVNpS0enfVYCWOGsVg a4vkisCJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYvpztQAKCRAk1otyXVSH0PR9B/ wMBUvHRaUFVi6tTbvXfN2YQlIMllyDawFEkgMl4381HnCAokkmULFhVaOouNBWflJq4I3BMLgY3eCj gCUUnHP8GdZL2vwcMM8EcH/io8znOm+77T4nivo++z0fQ1KH2wojMOy+ebe/Si0RwrJh/ciknFGrlK so6GTrVhn2cqKzwn7t18qC3Wp08ujTcu6m4O3PXnhO+pLXmcf+lHQZTLQLGjTm0nHHy0q9RqhVUcMy NWqwpqfR/UD6oGzjmsN9S9S+sSFIaldSofFNyGpA7cHLuAO8zrTHRApUSmFPmPxOt553TOzZohdhAS qLXIqzsvhrSeLpZkSReG7nJWP3xHEm X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220815_092729_930988_6ECB7F8C X-CRM114-Status: GOOD ( 16.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org For some reason we refer to ID_AA64MMFR0_EL1.ASIDBits as ASID. Add BITS into the name, bringing the naming into sync with DDI0487H.a. Due to the large amount of MixedCase in this register which isn't really consistent with either the kernel style or the majority of the architecture the use of upper case is preserved. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 6 +++--- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 2 +- arch/arm64/mm/context.c | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index cc70d0ebffa2..842b0cb8c4e2 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -745,11 +745,11 @@ #define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16 #define ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12 #define ID_AA64MMFR0_EL1_BIGEND_SHIFT 8 -#define ID_AA64MMFR0_EL1_ASID_SHIFT 4 +#define ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT 0 -#define ID_AA64MMFR0_EL1_ASID_8 0x0 -#define ID_AA64MMFR0_EL1_ASID_16 0x2 +#define ID_AA64MMFR0_EL1_ASIDBITS_8 0x0 +#define ID_AA64MMFR0_EL1_ASIDBITS_16 0x2 #define ID_AA64MMFR0_EL1_TGRAN4_NI 0xf #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 4c0bc39d1dc3..0d0b599fbfd5 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -352,7 +352,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { /* Linux shouldn't care about secure memory */ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASID_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), /* * Differing PARange is fine as long as all peripherals and memory are mapped * within the minimum PARange of all CPUs diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index 0ece26707fc0..0c2e474d0c9e 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -87,7 +87,7 @@ */ #define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\ FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASID), ID_AA64MMFR0_EL1_ASID_16) \ + FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \ ) /* diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 8f38a5452d05..e1e0dca01839 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -43,17 +43,17 @@ static u32 get_cpu_asid_bits(void) { u32 asid; int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1), - ID_AA64MMFR0_EL1_ASID_SHIFT); + ID_AA64MMFR0_EL1_ASIDBITS_SHIFT); switch (fld) { default: pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n", smp_processor_id(), fld); fallthrough; - case ID_AA64MMFR0_EL1_ASID_8: + case ID_AA64MMFR0_EL1_ASIDBITS_8: asid = 8; break; - case ID_AA64MMFR0_EL1_ASID_16: + case ID_AA64MMFR0_EL1_ASIDBITS_16: asid = 16; }