| Message ID | 20220817204357.21753-4-leoyang.li@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ls208xa dts updates | expand |
On Wed, Aug 17, 2022 at 03:43:54PM -0500, Li Yang wrote: > Define PHY nodes on the board. > > Signed-off-by: Li Yang <leoyang.li@nxp.com> > --- > .../boot/dts/freescale/fsl-ls2080a-rdb.dts | 68 +++++++++++++++++++ > 1 file changed, 68 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts > index 44894356059c..fec02fd754be 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts > @@ -23,3 +23,71 @@ chosen { > stdout-path = "serial1:115200n8"; > }; > }; > + > +&dpmac5 { > + phy-handle = <&mdio2_phy1>; > + phy-connection-type = "10gbase-r"; > +}; > + > +&dpmac6 { > + phy-handle = <&mdio2_phy2>; > + phy-connection-type = "10gbase-r"; > +}; > + > +&dpmac7 { > + phy-handle = <&mdio2_phy3>; > + phy-connection-type = "10gbase-r"; > +}; > + > +&dpmac8 { > + phy-handle = <&mdio2_phy4>; > + phy-connection-type = "10gbase-r"; > +}; > + > +&emdio1 { > + status = "disabled"; > + > + /* CS4340 PHYs */ > + mdio1_phy1: emdio1-phy@1 { > + reg = <0x10>; unit-address doesn't match 'reg'. > + }; > + > + mdio1_phy2: emdio1-phy@2 { > + reg = <0x11>; > + }; > + > + mdio1_phy3: emdio1-phy@3 { > + reg = <0x12>; > + }; > + > + mdio1_phy4: emdio1-phy@4 { > + reg = <0x13>; > + }; > +}; > + > +&emdio2 { > + /* AQR405 PHYs */ > + mdio2_phy1: emdio2-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c45"; > + interrupts = <0 1 0x4>; /* Level high type */ What does '0' mean here? And why not IRQ_TYPE_LEVEL_HIGH for polarity cell? Shawn > + reg = <0x0>; > + }; > + > + mdio2_phy2: emdio2-phy@2 { > + compatible = "ethernet-phy-ieee802.3-c45"; > + interrupts = <0 2 0x4>; /* Level high type */ > + reg = <0x1>; > + }; > + > + mdio2_phy3: emdio2-phy@3 { > + compatible = "ethernet-phy-ieee802.3-c45"; > + interrupts = <0 4 0x4>; /* Level high type */ > + reg = <0x2>; > + }; > + > + mdio2_phy4: emdio2-phy@4 { > + compatible = "ethernet-phy-ieee802.3-c45"; > + interrupts = <0 5 0x4>; /* Level high type */ > + reg = <0x3>; > + }; > +}; > -- > 2.37.1 >
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts index 44894356059c..fec02fd754be 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts @@ -23,3 +23,71 @@ chosen { stdout-path = "serial1:115200n8"; }; }; + +&dpmac5 { + phy-handle = <&mdio2_phy1>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac6 { + phy-handle = <&mdio2_phy2>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac7 { + phy-handle = <&mdio2_phy3>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac8 { + phy-handle = <&mdio2_phy4>; + phy-connection-type = "10gbase-r"; +}; + +&emdio1 { + status = "disabled"; + + /* CS4340 PHYs */ + mdio1_phy1: emdio1-phy@1 { + reg = <0x10>; + }; + + mdio1_phy2: emdio1-phy@2 { + reg = <0x11>; + }; + + mdio1_phy3: emdio1-phy@3 { + reg = <0x12>; + }; + + mdio1_phy4: emdio1-phy@4 { + reg = <0x13>; + }; +}; + +&emdio2 { + /* AQR405 PHYs */ + mdio2_phy1: emdio2-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 1 0x4>; /* Level high type */ + reg = <0x0>; + }; + + mdio2_phy2: emdio2-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; /* Level high type */ + reg = <0x1>; + }; + + mdio2_phy3: emdio2-phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 4 0x4>; /* Level high type */ + reg = <0x2>; + }; + + mdio2_phy4: emdio2-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 5 0x4>; /* Level high type */ + reg = <0x3>; + }; +};
Define PHY nodes on the board. Signed-off-by: Li Yang <leoyang.li@nxp.com> --- .../boot/dts/freescale/fsl-ls2080a-rdb.dts | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+)