| Message ID | 20220818140519.2767771-3-vladimir.oltean@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | NXP LS1028A DT changes for multiple switch CPU ports | expand |
Am 2022-08-18 16:05, schrieb Vladimir Oltean: > The LS1028A switch has 2 internal links to the ENETC controller. > > With DSA's ability to support multiple CPU ports, we should mark both > ENETC ports as DSA masters. > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > index 3da105119d82..455778936899 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > @@ -1170,6 +1170,7 @@ mscc_felix_port5: port@5 { > reg = <5>; > phy-mode = "internal"; > status = "disabled"; > + ethernet = <&enetc_port3>; status should be the last property, no? -michael
On Thu, Aug 18, 2022 at 04:44:28PM +0200, Michael Walle wrote:
> status should be the last property, no?
idk, should it?
Am 2022-08-18 16:45, schrieb Vladimir Oltean: > On Thu, Aug 18, 2022 at 04:44:28PM +0200, Michael Walle wrote: >> status should be the last property, no? > > idk, should it? IIRC Shawn pointed that out. If I'm mistaken, then do it for the consistency within fsl-ls1028a.dtsi :) -michael
On Thu, Aug 18, 2022 at 05:08:57PM +0200, Michael Walle wrote: > Am 2022-08-18 16:45, schrieb Vladimir Oltean: > > On Thu, Aug 18, 2022 at 04:44:28PM +0200, Michael Walle wrote: > > > status should be the last property, no? > > > > idk, should it? > > IIRC Shawn pointed that out. If I'm mistaken, then do it for the > consistency within fsl-ls1028a.dtsi :) Yeah, I prefer to have 'status' be the last. Shawn
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 3da105119d82..455778936899 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1170,6 +1170,7 @@ mscc_felix_port5: port@5 { reg = <5>; phy-mode = "internal"; status = "disabled"; + ethernet = <&enetc_port3>; fixed-link { speed = <1000>;
The LS1028A switch has 2 internal links to the ENETC controller. With DSA's ability to support multiple CPU ports, we should mark both ENETC ports as DSA masters. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 + 1 file changed, 1 insertion(+)