diff mbox series

[v4,5/8] arm64: dts: imx8mm-kontron: Remove low DDRC operating point

Message ID 20220822080357.24478-6-frieder@fris.de (mailing list archive)
State New, archived
Headers show
Series arm64: dts: imx8mm-kontron: Improvements and OSM board support | expand

Commit Message

Frieder Schrempf Aug. 22, 2022, 8:03 a.m. UTC 
From: Frieder Schrempf <frieder.schrempf@kontron.de>

For some reason there is a problem with finding a DDR configuration
that works on all operating points and all LPDDR4 types used on the
SoM. Therefore the bootloader currently doesn't configure the lowest
of the three operating points. Let's also skip this in the kernel
devicetree to make sure it isn't used.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
Changes in v4:
* none

Changes in v3:
* rebase on v6.0-rc1

Changes in v2:
* none
---
 arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi | 4 ----
 1 file changed, 4 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi
index 33179157f619..96ecdce67059 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi
@@ -46,10 +46,6 @@  &ddrc {
 	ddrc_opp_table: opp-table {
 		compatible = "operating-points-v2";
 
-		opp-25M {
-			opp-hz = /bits/ 64 <25000000>;
-		};
-
 		opp-100M {
 			opp-hz = /bits/ 64 <100000000>;
 		};