From patchwork Mon Aug 22 19:07:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12951279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DAE55C32774 for ; Mon, 22 Aug 2022 19:26:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qo2xaYNsOTEIU9gzMqYiAleGCcYWtSo9rfQTYot/ze4=; b=0qNoC9spVYx4mM Kej1rcWRedTtxzOHnioSlm2ggm0YnTyesp8id02sqaSGkDdfw4bqiqVnP4KyIzld3H8sQajmq23rG JjUVBjUQ9AZuO97L7NO8gVWCF4AI4IdB0tYv3PGSyjKWi9P4HFrXs2qSjjfl/zyFeI2bTi8CObXpA xBrrLIeKkANMZAyEo5bN8sUT6TWpzCuoL6UWhtSrk3WkHAvjtlX6FMu3xctqcc1dtbIZ1acb9rsB8 wiyV5tN/HUhSKkpNsg3AbDGOQ2Efp/Zt+xFDPih/23dkmvid/9onJmVbyPZofvQmNVWMSXhz/6kgY D4+KVwwAhnFCBBsu3dcQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQD2U-00E136-Cr; Mon, 22 Aug 2022 19:24:46 +0000 Received: from mail.baikalelectronics.com ([87.245.175.230]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQCmX-00Ds8D-Ts for linux-arm-kernel@lists.infradead.org; Mon, 22 Aug 2022 19:08:21 +0000 Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 921DADB5; Mon, 22 Aug 2022 22:11:01 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 921DADB5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1661195461; bh=wKkcN3HZX1AdoJ6/AuZ/ZUEzqQK3g/fN1ZxHj04NS0w=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Z0oBWhAAsn4j8h+pkCJjO7PLszrppdjFAm2Q60n1w3krhgHAldy3HEuiLEsGG+YHp YLRLOHJmLkEEow6sc5rmdlAHZah7r7YYur8fOaF2tkVViQYAxMuE+gfwOpibbX0Sj6 KRvJp28HHaVQPUUvRuYUhRZFpsJXAYH9dEnAedU4= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 22 Aug 2022 22:07:47 +0300 From: Serge Semin To: Rob Herring , Michal Simek , Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , James Morse , Robert Richter CC: Serge Semin , Serge Semin , Alexey Malahov , Michail Ivanov , Pavel Parkhomenko , Punnaiah Choudary Kalluri , Manish Narani , Dinh Nguyen , Rob Herring , Krzysztof Kozlowski , , , , Subject: [PATCH 20/20] EDAC/synopsys: Convert to using BIT/GENMASK/FIELD_x macros Date: Mon, 22 Aug 2022 22:07:30 +0300 Message-ID: <20220822190730.27277-21-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220822190730.27277-1-Sergey.Semin@baikalelectronics.ru> References: <20220822190730.27277-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220822_120818_391453_7DE1528B X-CRM114-Status: GOOD ( 16.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Instead of using the very handy helpers denoted in the subject the driver has been created with the open-coded {mask,shift} statements. It makes the code bulky, prone to mistakes and much harder to read. Seeing there are many places in the driver implementing the CSR fields get/set pattern let's use the FIELD_GET()/FIELD_PREP() macros introduced in the kernel specifically for that case. In addition we suggest to use the BIT() and GENMASK() macros to generate the CSR flags/masks. While at it unify the row, column, rank, bank and bank group macros names to be looking in the same way as the fields of the snps_ecc_error_info structure. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 124 +++++++++++++++++------------------ 1 file changed, 61 insertions(+), 63 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 9ac0c8c4e3b8..bcef9672f700 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -6,6 +6,8 @@ * Copyright (C) 2012 - 2014 Xilinx, Inc. */ +#include +#include #include #include #include @@ -90,22 +92,19 @@ #define DDR_MSTR_DEV_X8 0x1 #define DDR_MSTR_DEV_X16 0x2 #define DDR_MSTR_DEV_X32 0x3 -#define DDR_MSTR_BUSWIDTH_MASK 0x3000 -#define DDR_MSTR_BUSWIDTH_SHIFT 12 +#define DDR_MSTR_BUSWIDTH_MASK GENMASK(13, 12) #define DDRCTL_EWDTH_16 2 #define DDRCTL_EWDTH_32 1 #define DDRCTL_EWDTH_64 0 /* ECC CFG0 register definitions */ -#define ECC_CFG0_MODE_MASK 0x7 +#define ECC_CFG0_MODE_MASK GENMASK(2, 0) #define ECC_CFG0_MODE_SECDED 0x4 /* ECC status register definitions */ -#define ECC_STAT_UECNT_MASK 0xF0000 -#define ECC_STAT_UECNT_SHIFT 16 -#define ECC_STAT_CECNT_MASK 0xF00 -#define ECC_STAT_CECNT_SHIFT 8 -#define ECC_STAT_BITNUM_MASK 0x7F +#define ECC_STAT_UE_MASK GENMASK(23, 16) +#define ECC_STAT_CE_MASK GENMASK(15, 8) +#define ECC_STAT_BITNUM_MASK GENMASK(6, 0) /* ECC control/clear register definitions */ #define ECC_CTRL_CLR_CE_ERR BIT(0) @@ -116,49 +115,41 @@ #define ECC_CTRL_EN_UE_IRQ BIT(9) /* ECC error count register definitions */ -#define ECC_ERRCNT_UECNT_MASK 0xFFFF0000 -#define ECC_ERRCNT_UECNT_SHIFT 16 -#define ECC_ERRCNT_CECNT_MASK 0xFFFF +#define ECC_ERRCNT_UECNT_MASK GENMASK(31, 16) +#define ECC_ERRCNT_CECNT_MASK GENMASK(15, 0) /* DDR QOS Interrupt register definitions */ #define DDR_QOS_IRQ_STAT_OFST 0x20200 -#define DDR_QOSUE_MASK 0x4 -#define DDR_QOSCE_MASK 0x2 -#define ECC_CE_UE_INTR_MASK 0x6 +#define DDR_QOSUE_MASK BIT(2) +#define DDR_QOSCE_MASK BIT(1) +#define ECC_CE_UE_INTR_MASK (DDR_QOSUE_MASK | DDR_QOSCE_MASK) #define DDR_QOS_IRQ_EN_OFST 0x20208 #define DDR_QOS_IRQ_DB_OFST 0x2020C /* ECC Corrected Error Register Mask and Shifts*/ -#define ECC_CEADDR0_RW_MASK 0x3FFFF -#define ECC_CEADDR0_RNK_MASK BIT(24) -#define ECC_CEADDR1_BNKGRP_MASK 0x3000000 -#define ECC_CEADDR1_BNKNR_MASK 0x70000 -#define ECC_CEADDR1_COL_MASK 0xFFF -#define ECC_CEADDR1_BNKGRP_SHIFT 24 -#define ECC_CEADDR1_BNKNR_SHIFT 16 +#define ECC_CEADDR0_RANK_MASK GENMASK(27, 24) +#define ECC_CEADDR0_ROW_MASK GENMASK(17, 0) +#define ECC_CEADDR1_BANKGRP_MASK GENMASK(25, 24) +#define ECC_CEADDR1_BANK_MASK GENMASK(23, 16) +#define ECC_CEADDR1_COL_MASK GENMASK(11, 0) /* ECC Poison register shifts */ -#define ECC_POISON0_RANK_SHIFT 24 -#define ECC_POISON0_RANK_MASK BIT(24) -#define ECC_POISON0_COLUMN_SHIFT 0 -#define ECC_POISON0_COLUMN_MASK 0xFFF -#define ECC_POISON1_BG_SHIFT 28 -#define ECC_POISON1_BG_MASK 0x30000000 -#define ECC_POISON1_BANKNR_SHIFT 24 -#define ECC_POISON1_BANKNR_MASK 0x7000000 -#define ECC_POISON1_ROW_SHIFT 0 -#define ECC_POISON1_ROW_MASK 0x3FFFF +#define ECC_POISON0_RANK_MASK GENMASK(27, 24) +#define ECC_POISON0_COL_MASK GENMASK(11, 0) +#define ECC_POISON1_BANKGRP_MASK GENMASK(29, 28) +#define ECC_POISON1_BANK_MASK GENMASK(26, 24) +#define ECC_POISON1_ROW_MASK GENMASK(17, 0) /* DDR Memory type defines */ -#define MEM_TYPE_DDR3 0x1 -#define MEM_TYPE_LPDDR3 0x8 -#define MEM_TYPE_DDR2 0x4 -#define MEM_TYPE_DDR4 0x10 -#define MEM_TYPE_LPDDR4 0x20 +#define MEM_TYPE_DDR3 BIT(0) +#define MEM_TYPE_DDR2 BIT(2) +#define MEM_TYPE_LPDDR3 BIT(3) +#define MEM_TYPE_DDR4 BIT(4) +#define MEM_TYPE_LPDDR4 BIT(5) /* DDRC ECC CE & UE poison mask */ -#define ECC_CEPOISON_MASK 0x3 -#define ECC_UEPOISON_MASK 0x1 +#define ECC_CEPOISON_MASK GENMASK(1, 0) +#define ECC_UEPOISON_MASK BIT(0) /* DDRC Device config shifts/masks */ #define DDR_MAX_ROW_SHIFT 18 @@ -303,38 +294,40 @@ static int snps_get_error_info(struct snps_edac_priv *priv) if (!regval) return 1; - p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); + p->ceinfo.bitpos = FIELD_GET(ECC_STAT_BITNUM_MASK, regval); regval = readl(base + ECC_ERRCNT_OFST); - p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; - p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; + p->ce_cnt = FIELD_GET(ECC_ERRCNT_CECNT_MASK, regval); + p->ue_cnt = FIELD_GET(ECC_ERRCNT_UECNT_MASK, regval); if (!p->ce_cnt) goto ue_err; regval = readl(base + ECC_CEADDR0_OFST); - p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); + p->ceinfo.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval); + regval = readl(base + ECC_CEADDR1_OFST); - p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> - ECC_CEADDR1_BNKNR_SHIFT; - p->ceinfo.bankgrp = (regval & ECC_CEADDR1_BNKGRP_MASK) >> - ECC_CEADDR1_BNKGRP_SHIFT; - p->ceinfo.col = (regval & ECC_CEADDR1_COL_MASK); + p->ceinfo.bank = FIELD_GET(ECC_CEADDR1_BANK_MASK, regval); + p->ceinfo.bankgrp = FIELD_GET(ECC_CEADDR1_BANKGRP_MASK, regval); + p->ceinfo.col = FIELD_GET(ECC_CEADDR1_COL_MASK, regval); + p->ceinfo.data = readl(base + ECC_CSYND0_OFST); + edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n", readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST), readl(base + ECC_CSYND2_OFST)); + ue_err: if (!p->ue_cnt) goto out; regval = readl(base + ECC_UEADDR0_OFST); - p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); + p->ueinfo.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval); + regval = readl(base + ECC_UEADDR1_OFST); - p->ueinfo.bankgrp = (regval & ECC_CEADDR1_BNKGRP_MASK) >> - ECC_CEADDR1_BNKGRP_SHIFT; - p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> - ECC_CEADDR1_BNKNR_SHIFT; - p->ueinfo.col = (regval & ECC_CEADDR1_COL_MASK); + p->ueinfo.bankgrp = FIELD_GET(ECC_CEADDR1_BANKGRP_MASK, regval); + p->ueinfo.bank = FIELD_GET(ECC_CEADDR1_BANK_MASK, regval); + p->ueinfo.col = FIELD_GET(ECC_CEADDR1_COL_MASK, regval); + p->ueinfo.data = readl(base + ECC_UESYND0_OFST); out: @@ -509,7 +502,8 @@ static bool snps_get_ecc_state(void __iomem *base) { u32 regval; - regval = readl(base + ECC_CFG0_OFST) & ECC_CFG0_MODE_MASK; + regval = readl(base + ECC_CFG0_OFST); + regval = FIELD_GET(ECC_CFG0_MODE_MASK, regval); return (regval == ECC_CFG0_MODE_SECDED); } @@ -699,13 +693,13 @@ static void snps_data_poison_setup(struct snps_edac_priv *priv) if (priv->rank_shift[0]) rank = (hif_addr >> priv->rank_shift[0]) & BIT(0); - regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK; - regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK; + regval = FIELD_PREP(ECC_POISON0_RANK_MASK, rank) | + FIELD_PREP(ECC_POISON0_COL_MASK, col); writel(regval, priv->baseaddr + ECC_POISON0_OFST); - regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK; - regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK; - regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK; + regval = FIELD_PREP(ECC_POISON1_BANKGRP_MASK, bankgrp) | + FIELD_PREP(ECC_POISON1_BANK_MASK, bank) | + FIELD_PREP(ECC_POISON1_ROW_MASK, row); writel(regval, priv->baseaddr + ECC_POISON1_OFST); } @@ -744,10 +738,14 @@ static ssize_t inject_data_poison_show(struct device *dev, { struct mem_ctl_info *mci = to_mci(dev); struct snps_edac_priv *priv = mci->pvt_info; + const char *errstr; + u32 regval; + + regval = readl(priv->baseaddr + ECC_CFG1_OFST); + errstr = FIELD_GET(ECC_CEPOISON_MASK, regval) == ECC_CEPOISON_MASK ? + "Correctable Error" : "UnCorrectable Error"; - return sprintf(data, "Data Poisoning: %s\n\r", - (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3) - ? ("Correctable Error") : ("UnCorrectable Error")); + return sprintf(data, "Data Poisoning: %s\n\r", errstr); } static ssize_t inject_data_poison_store(struct device *dev, @@ -854,7 +852,7 @@ static void snps_setup_column_address_map(struct snps_edac_priv *priv, u32 *addr int index; memtype = readl(priv->baseaddr + DDR_MSTR_OFST); - width = (memtype & DDR_MSTR_BUSWIDTH_MASK) >> DDR_MSTR_BUSWIDTH_SHIFT; + width = FIELD_GET(DDR_MSTR_BUSWIDTH_MASK, memtype); priv->col_shift[0] = 0; priv->col_shift[1] = 1;