@@ -107,6 +107,25 @@ static int sgmii_pcs_scratch_test(struct altera_tse_private *priv, u16 value)
return (sgmii_pcs_read(priv, SGMII_PCS_SCRATCH) == value);
}
+static int sgmii_pcs_reset(struct altera_tse_private *priv)
+{
+ u16 bmcr;
+ int i = 0;
+
+ /* Reset PCS block */
+ bmcr = sgmii_pcs_read(priv, MII_BMCR);
+ bmcr |= BMCR_RESET;
+ sgmii_pcs_write(priv, MII_BMCR, bmcr);
+
+ for (i = 0; i < SGMII_PCS_SW_RESET_TIMEOUT; i++) {
+ if (!(sgmii_pcs_read(priv, MII_BMCR) & BMCR_RESET))
+ return 0;
+ udelay(1);
+ }
+
+ return -ETIMEDOUT;
+}
+
/* MDIO specific functions
*/
static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
@@ -1092,7 +1111,6 @@ static void tse_set_rx_mode(struct net_device *dev)
static int init_sgmii_pcs(struct net_device *dev)
{
struct altera_tse_private *priv = netdev_priv(dev);
- int n;
unsigned int tmp_reg = 0;
if (priv->phy_iface != PHY_INTERFACE_MODE_SGMII)
@@ -1131,20 +1149,7 @@ static int init_sgmii_pcs(struct net_device *dev)
tmp_reg |= (BMCR_SPEED1000 | BMCR_FULLDPLX | BMCR_ANENABLE);
sgmii_pcs_write(priv, MII_BMCR, tmp_reg);
- /* Reset PCS block */
- tmp_reg |= BMCR_RESET;
- sgmii_pcs_write(priv, MII_BMCR, tmp_reg);
- for (n = 0; n < SGMII_PCS_SW_RESET_TIMEOUT; n++) {
- if (!(sgmii_pcs_read(priv, MII_BMCR) & BMCR_RESET)) {
- netdev_info(dev, "SGMII PCS block initialised OK\n");
- return 0;
- }
- udelay(1);
- }
-
- /* We failed to reset the block, return a timeout */
- netdev_err(dev, "SGMII PCS block reset failed.\n");
- return -ETIMEDOUT;
+ return sgmii_pcs_reset(priv);
}
/* Open and initialize the interface
Performing a soft reset on the PCS block for altera TSE re-initializes the decoding logic, and should be done when reconfiguring the link. Move the reset logic to a dedicated helper, to ease transition to phylink. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> --- drivers/net/ethernet/altera/altera_tse_main.c | 35 +++++++++++-------- 1 file changed, 20 insertions(+), 15 deletions(-)