diff mbox series

[2/3] soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PD

Message ID 20220826191305.3215706-2-l.stach@pengutronix.de (mailing list archive)
State New, archived
Headers show
Series [1/3] soc: imx: imx8mp-blk-ctrl: don't set power device name in | expand

Commit Message

Lucas Stach Aug. 26, 2022, 7:13 p.m. UTC 
NXP internal information shows that the PHY refclk is gated by the
GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the
LCDIF being already active, tie this bit to the HDMI_TX_PHY power
domain.

Fixes: e3442022f543 ("soc: imx: add i.MX8MP HDMI blk-ctrl")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8mp-blk-ctrl.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Peng Fan Aug. 29, 2022, 1:56 a.m. UTC | #1 
+ Sandor

> Subject: [PATCH 2/3] soc: imx: imx8mp-blk-ctrl: enable global pixclk with
> HDMI_TX_PHY PD
> 
> NXP internal information shows that the PHY refclk is gated by the
> GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the
> LCDIF being already active, tie this bit to the HDMI_TX_PHY power domain.
> 
> Fixes: e3442022f543 ("soc: imx: add i.MX8MP HDMI blk-ctrl")
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/soc/imx/imx8mp-blk-ctrl.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-
> blk-ctrl.c
> index 9401df25c85a..73f672104aaa 100644
> --- a/drivers/soc/imx/imx8mp-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
> @@ -192,7 +192,7 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct
> imx8mp_blk_ctrl *bc,
>  		break;
>  	case IMX8MP_HDMIBLK_PD_LCDIF:
>  		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
> -				BIT(7) | BIT(16) | BIT(17) | BIT(18) |
> +				BIT(16) | BIT(17) | BIT(18) |
>  				BIT(19) | BIT(20));
>  		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
> BIT(11));
>  		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, @@
> -221,6 +221,7 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct
> imx8mp_blk_ctrl *bc,
>  		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
>  		break;
>  	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
> +		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
>  		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22)
> | BIT(24));
>  		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
> BIT(12));
>  		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0,
> BIT(3)); @@ -243,7 +244,7 @@ static void
> imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
>  				  BIT(4) | BIT(5) | BIT(6));
>  		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
> BIT(11));
>  		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
> -				  BIT(7) | BIT(16) | BIT(17) | BIT(18) |
> +				  BIT(16) | BIT(17) | BIT(18) |
>  				  BIT(19) | BIT(20));
>  		break;
>  	case IMX8MP_HDMIBLK_PD_PAI:
> @@ -271,6 +272,7 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct
> imx8mp_blk_ctrl *bc,
>  	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
>  		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
>  		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
> BIT(12));
> +		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
> BIT(7));
>  		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
> BIT(22) | BIT(24));
>  		break;
>  	default:
> --
> 2.30.2
Lucas Stach Dec. 15, 2022, 3:09 p.m. UTC | #2 
Hi Shawn, Peng,

Am Montag, dem 29.08.2022 um 01:56 +0000 schrieb Peng Fan:
> + Sandor
> 
Could you please pull this patch in? It's based on information I got
from Sandor.

Regards,
Lucas

> > Subject: [PATCH 2/3] soc: imx: imx8mp-blk-ctrl: enable global pixclk with
> > HDMI_TX_PHY PD
> > 
> > NXP internal information shows that the PHY refclk is gated by the
> > GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the
> > LCDIF being already active, tie this bit to the HDMI_TX_PHY power domain.
> > 
> > Fixes: e3442022f543 ("soc: imx: add i.MX8MP HDMI blk-ctrl")
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> >  drivers/soc/imx/imx8mp-blk-ctrl.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-
> > blk-ctrl.c
> > index 9401df25c85a..73f672104aaa 100644
> > --- a/drivers/soc/imx/imx8mp-blk-ctrl.c
> > +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
> > @@ -192,7 +192,7 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct
> > imx8mp_blk_ctrl *bc,
> >  		break;
> >  	case IMX8MP_HDMIBLK_PD_LCDIF:
> >  		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
> > -				BIT(7) | BIT(16) | BIT(17) | BIT(18) |
> > +				BIT(16) | BIT(17) | BIT(18) |
> >  				BIT(19) | BIT(20));
> >  		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
> > BIT(11));
> >  		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, @@
> > -221,6 +221,7 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct
> > imx8mp_blk_ctrl *bc,
> >  		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
> >  		break;
> >  	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
> > +		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
> >  		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22)
> > > BIT(24));
> >  		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
> > BIT(12));
> >  		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0,
> > BIT(3)); @@ -243,7 +244,7 @@ static void
> > imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
> >  				  BIT(4) | BIT(5) | BIT(6));
> >  		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
> > BIT(11));
> >  		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
> > -				  BIT(7) | BIT(16) | BIT(17) | BIT(18) |
> > +				  BIT(16) | BIT(17) | BIT(18) |
> >  				  BIT(19) | BIT(20));
> >  		break;
> >  	case IMX8MP_HDMIBLK_PD_PAI:
> > @@ -271,6 +272,7 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct
> > imx8mp_blk_ctrl *bc,
> >  	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
> >  		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
> >  		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
> > BIT(12));
> > +		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
> > BIT(7));
> >  		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
> > BIT(22) | BIT(24));
> >  		break;
> >  	default:
> > --
> > 2.30.2
>
Shawn Guo Dec. 31, 2022, 5:41 a.m. UTC | #3 
On Fri, Aug 26, 2022 at 09:13:04PM +0200, Lucas Stach wrote:
> NXP internal information shows that the PHY refclk is gated by the
> GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the
> LCDIF being already active, tie this bit to the HDMI_TX_PHY power
> domain.
> 
> Fixes: e3442022f543 ("soc: imx: add i.MX8MP HDMI blk-ctrl")
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Applied, thanks!
diff mbox series

Patch

diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 9401df25c85a..73f672104aaa 100644
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -192,7 +192,7 @@  static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
 		break;
 	case IMX8MP_HDMIBLK_PD_LCDIF:
 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
-				BIT(7) | BIT(16) | BIT(17) | BIT(18) |
+				BIT(16) | BIT(17) | BIT(18) |
 				BIT(19) | BIT(20));
 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
@@ -221,6 +221,7 @@  static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
 		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
 		break;
 	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
 		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
@@ -243,7 +244,7 @@  static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
 				  BIT(4) | BIT(5) | BIT(6));
 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
-				  BIT(7) | BIT(16) | BIT(17) | BIT(18) |
+				  BIT(16) | BIT(17) | BIT(18) |
 				  BIT(19) | BIT(20));
 		break;
 	case IMX8MP_HDMIBLK_PD_PAI:
@@ -271,6 +272,7 @@  static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
 	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
 		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
 		break;
 	default: