From patchwork Thu Sep 1 13:26:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 12962649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7730FC0502C for ; Thu, 1 Sep 2022 13:36:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IOhHvCpydwiPu7lJKH9b8kHCI9ZKoLDsRl6l591tQK4=; b=SbFifa5RN2N6ay JyvuM8oHWnUTHn2+DSgwZXfreHU7HEmek9OcOevD/4UHf/0O8j4rewsgF95SF62KnR31NALV8Jq2w qmz5Nj8NOSKYA0pZHKgwJ0VKzm3/y1a4ItI+ItQCzMDDWmtzE1mXA8+ZDEICUM36/dZQU3Jb7m4FC 1euGJjSyAHh4kSyFfwNGGlggc1fLxT2u8zjgjZh8Ng9q5QwWefgxeeF7tTDHYRLXQgsJldmDdXGCC UTl44X5VC308E7RagmuFOVG3l7pBcwhZxRwMQZmmWq39FyBgYMZZ4aZIjIjButYRA4oF0AO2w6gGq VjYQCmJ1u54PhThaw9Bg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTkLy-00C681-51; Thu, 01 Sep 2022 13:35:30 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTkEI-00C28f-4a for linux-arm-kernel@lists.infradead.org; Thu, 01 Sep 2022 13:27:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4438D1042; Thu, 1 Sep 2022 06:27:38 -0700 (PDT) Received: from e121896.arm.com (unknown [10.57.16.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7085E3F7B4; Thu, 1 Sep 2022 06:27:58 -0700 (PDT) From: James Clark To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, broonie@kernel.org, acme@kernel.org, leo.yan@linaro.org, john.garry@huawei.com, catalin.marinas@arm.com, will@kernel.org, James Clark , Jonathan Corbet , Mark Rutland , linux-doc@vger.kernel.org Subject: [PATCH v3 2/2] arm64/sve: Add Perf extensions documentation Date: Thu, 1 Sep 2022 14:26:58 +0100 Message-Id: <20220901132658.1024635-3-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220901132658.1024635-1-james.clark@arm.com> References: <20220901132658.1024635-1-james.clark@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220901_062734_260241_B29DB695 X-CRM114-Status: GOOD ( 13.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document that the VG register is available in Perf samples Signed-off-by: James Clark Reviewed-by: Mark Brown --- Documentation/arm64/sve.rst | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst index 93c2c2990584..8955bf1bf757 100644 --- a/Documentation/arm64/sve.rst +++ b/Documentation/arm64/sve.rst @@ -452,6 +452,24 @@ The regset data starts with struct user_sve_header, containing: * Modifying the system default vector length does not affect the vector length of any existing process or thread that does not make an execve() call. +10. Perf extensions +-------------------------------- + +* The arm64 specific DWARF standard [5] added the VG (Vector Granule) register + at index 46. This register is used for DWARF unwinding when variable length + SVE registers are pushed onto the stack. + +* Its value is equivalent to the current SVE vector length (VL) in bits divided + by 64. + +* The value is included in Perf samples in the regs[46] field if + PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 set. + +* The value is the current value at the time the sample was taken, and it can + change over time. + +* If the system doesn't support SVE when perf_event_open is called with these + settings, the event will fail to open. Appendix A. SVE programmer's model (informative) ================================================= @@ -593,3 +611,5 @@ References http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html Procedure Call Standard for the ARM 64-bit Architecture (AArch64) + +[5] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst