From patchwork Tue Sep 6 13:55:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7231ECAAD5 for ; Tue, 6 Sep 2022 14:54:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5JQR7qPjMdEZpkrokbg10vJVUL36BFVz2/dHj9OcQbE=; b=FG6iExqnhplF/h hTfJagClRrroUfMkkkrvKjEl1Gi0JUyx+5JIgU3Dc4J0gLOo3rVC/ryKZPUYmu5vYWnaGaMVb3ATm SLFzIslL8/HIji7KDu6MxmCkA5NZtUai9cayU4HJjtpbMIbxWdQ5oYbZLB/2OCBS+8W9mFuCx6QNe zV+fsGEXO+UYHaz3P3gcmLFeEw0qmm3AU/2MJ7cieY+iFqZanQAGLjQvKi0byNmiYWnywvgN3kJ9b ZCYYAsI3O/3KbRkIQO564wq1/U4cQGTQe2G2tpJ+HzW2GeDnl08eQR2n8htj9ksZ8/4Zs/JKUtvI2 Ttevgu/+zP0WA6SU1t4A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oVZwk-00ETPm-2x; Tue, 06 Sep 2022 14:53:03 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oVZ57-00E4Xa-1c for linux-arm-kernel@lists.infradead.org; Tue, 06 Sep 2022 13:57:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662472656; x=1694008656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0iBvNvc6oWFi2GwjYfyBen8v+JZc1cmnAG1OVejo090=; b=Da4TC2CIV9mab9c0lGNupAJu4n61IHJySuUuLCwsFVprLjzjovKUR9dj lMqefWx+R+3FIVcJi58Fk8Bl7k49qjCMC0Z8x/p3s4oJFcjtKJClypiEt LrF62jx/p6TFjGCmxy+VdP62UAxsSX30FJPDSLm3puY8clUUQl9Hfr31J edeho1vULVicJ6YViuPi96t2a7yRB88BrU66eBkzCiDwXZWW3eoRFYocK NNcuHkJG6bKcyjshTnMzCJDLqU7Z9BA5zsA0WU00102ygZevaHVjB8VTp EPJQtU6CAmWjE25S/ClszrLpR4eB6PkNFyYhK10EtsQ9BNkzPQgC35BwE Q==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="175830176" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:57:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:57:31 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:57:26 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 11/13] clk: at91: sama5d2: Add Generic Clocks for UART/USART Date: Tue, 6 Sep 2022 16:55:10 +0300 Message-ID: <20220906135511.144725-12-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220906_065737_195515_06295B41 X-CRM114-Status: UNSURE ( 9.86 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the generic clocks for UART/USART in the sama5d2 driver to allow them to be registered in the Common Clock Framework. Signed-off-by: Sergiu Moga Reviewed-by: Claudiu Beznea --- v1 -> v2: - Added R-b tag drivers/clk/at91/sama5d2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index cfd0f5e23b99..84156dc52bff 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -120,6 +120,16 @@ static const struct { struct clk_range r; int chg_pid; } sama5d2_gck[] = { + { .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart3_gclk", .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart4_gclk", .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, }, { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, }, { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },