| Message ID | 20220908150658.1839520-3-kavyasree.kotagiri@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for lan966x flexcom chip-select configuration | expand |
On 08/09/2022 17:06, Kavyasree Kotagiri wrote: > LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 > in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins > can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on > functions being configured. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. https://elixir.bootlin.com/linux/v5.17/source/Documentation/process/submitting-patches.rst#L540 If a tag was not added on purpose, please state why and what changed. Best regards, Krzysztof
> > On 08/09/2022 17:06, Kavyasree Kotagiri wrote: > > LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 > > in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins > > can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage > depends on > > functions being configured. > > > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > > Please add Acked-by/Reviewed-by tags when posting new versions. > However, > there's no need to repost patches *only* to add the tags. The upstream > maintainer will do that for acks received on the version they apply. > > https://elixir.bootlin.com/linux/v5.17/source/Documentation/process/subm > itting-patches.rst#L540 > > If a tag was not added on purpose, please state why and what changed. > Yes, You are right. I missed adding reviewed-by tag for 2/3 and 3/3 patches(which doesn't have any issues while applying on latest version) I haven't added tag for patch-1/3 as there is small change (i.e., Changed reference provided for spi bindings to atmel,at91rm9200-spi.yaml) while applying changes on latest version. > > Best regards, > Krzysztof
diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 63849dacefb8..e158af47c326 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -18,9 +18,11 @@ properties: compatible: enum: - atmel,sama5d2-flexcom + - microchip,lan9668-flexcom reg: - maxItems: 1 + minItems: 1 + maxItems: 2 clocks: maxItems: 1 @@ -47,6 +49,27 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 3] + microchip,flx-shrd-pins: + description: Specify the Flexcom shared pins to be used for flexcom + chip-selects. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 20 + + microchip,flx-cs: + description: Flexcom chip selects. Here, value of '0' represents "cts" line + of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents + "rts" line of flexcom USART or "cs1" line of flexcom SPI. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + patternProperties: "^serial@[0-9a-f]+$": type: object @@ -73,6 +96,31 @@ required: - ranges - atmel,flexcom-mode +allOf: + - if: + properties: + compatible: + contains: + const: microchip,lan9668-flexcom + + then: + properties: + reg: + items: + - description: Flexcom base registers map + - description: Flexcom shared registers map + required: + - microchip,flx-shrd-pins + - microchip,flx-cs + + else: + properties: + reg: + items: + - description: Flexcom base registers map + microchip,flx-shrd-pins: false + microchip,flx-cs: false + additionalProperties: false examples: @@ -88,4 +136,19 @@ examples: ranges = <0x0 0xf8034000 0x800>; atmel,flexcom-mode = <2>; }; + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + flx3: flexcom@e0064000 { + compatible = "microchip,lan9668-flexcom"; + reg = <0xe0064000 0x100>, + <0xe2004180 0x8>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + atmel,flexcom-mode = <2>; + microchip,flx-shrd-pins = <9>; + microchip,flx-cs = <0>; + }; ...
LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on functions being configured. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> --- v8 -> v9: - No changes. v7 -> v8: - Changed compatible string to microchip,lan9668-flexcom. v6 -> v7: - Add #address-cells, #size-cells to flx3 example. v5 -> v6: - Removed spi node from flx3 example. v4 -> v5: - Fixed indentations and dt-schema errors. - No errors seen with 'make dt_binding_check'. v3 -> v4: - Added else condition to allOf:if:then. v2 -> v3: - Add reg property of lan966x missed in v2. v1 -> v2: - Use allOf:if:then for lan966x dt properties .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 65 ++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-)