From patchwork Wed Sep 21 03:13:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 12983103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5D85C6FA82 for ; Wed, 21 Sep 2022 03:15:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6uHnPZxNjP62ujiU0VHf3HKW6K2JatQaoysOdyOOuXU=; b=GjXYZT338Oalbp ub1Sk0qN1KBJRyQzBansVDbwQnGT5MexgfjNema+GccTD/mHgar1HRZ9NbRDqnGuQ+A0vLuSU+eKM 8iFQcf+ZMXgRDdNf4Twmyd32v/j3jg2zZnw8o69g2PxUuNfXn6E5XtHFxec5l/x8S38mMbbAxyQwM 0Z/ynXl1yCLcEO8CDLxH3p9m85M9PYfAl8+lyP/K/4Gsvfyo1/zzj0FKcf/55HfAU9zvIy5km2B1I FBq7wp88Z0IIfGiFhbRyLwr3cahknNDWpMcugj2UZXw2r1ZQmO4sgN2CA4X/5379x5zgIDgXqxua1 /zL2X7TWt/DR4Y1t0QDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oaqC7-008Sff-5r; Wed, 21 Sep 2022 03:14:39 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oaqBL-008SQk-8t for linux-arm-kernel@lists.infradead.org; Wed, 21 Sep 2022 03:13:53 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28L3Db5M049714; Tue, 20 Sep 2022 22:13:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663730017; bh=N6qozps8bDMn9lW8NQSWgT9uC5bba9QSDWJQchNs+BI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eGVoHzLC5zDo4k7qzweONJ3gQATe5JRlOQJujxwBjivNLmDRZ2VkrEA805OIiGSvU y88xMS3fABCcy5Dd+2EH3RPchDrkrKIKri6+6cbuVBTdv6YaUzkk5UFftfuOYnDf+p QM7itrSsYa0jbttNSMyGhPb44DDDaOUqWyElFcXg= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28L3DbL5083406 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Sep 2022 22:13:37 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 20 Sep 2022 22:13:37 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 20 Sep 2022 22:13:37 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28L3DYHJ010818; Tue, 20 Sep 2022 22:13:36 -0500 From: Matt Ranostay To: , , CC: , , , Matt Ranostay Subject: [PATCH v3 2/9] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Date: Tue, 20 Sep 2022 20:13:20 -0700 Message-ID: <20220921031327.4135-3-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220921031327.4135-1-mranostay@ti.com> References: <20220921031327.4135-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220920_201351_490649_64E8F4D2 X-CRM114-Status: GOOD ( 11.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Cc: Vignesh Raghavendra Cc: Nishanth Menon Signed-off-by: Matt Ranostay --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 1f178ad3fa42..a4260ffb75c7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -5,6 +5,16 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -38,6 +48,13 @@ usb_serdes_mux: mux-controller-0 { #mux-control-cells = <1>; mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; + + serdes_ln_ctrl: mux-controller-80 { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; }; gic500: interrupt-controller@1800000 { @@ -728,6 +745,42 @@ usb0: usb@6000000 { }; }; + serdes_wiz0: wiz@5060000 { + compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 365 3>; + assigned-clock-parents = <&k3_clks 365 7>; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>,