diff mbox series

[v1,5/8] arm64: dts: verdin-imx8mm: improve pcie node

Message ID 20220922162925.2368577-6-marcel@ziswiler.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: verdin-imx8mm: verdin-imx8mp: pcie. et. al. | expand

Commit Message

Marcel Ziswiler Sept. 22, 2022, 4:29 p.m. UTC 
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Slight improvement of pcie node to be more in-line with what we add on
the Verdin iMX8M Plus.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

 arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Shawn Guo Oct. 23, 2022, 1:11 p.m. UTC | #1 
On Thu, Sep 22, 2022 at 06:29:22PM +0200, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> Slight improvement of pcie node to be more in-line with what we add on
> the Verdin iMX8M Plus.
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 0c2582402087..0f1c6e320c66 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -638,7 +638,8 @@  &pcie0 {
 	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 				 <&clk IMX8MM_SYS_PLL2_250M>;
 	assigned-clock-rates = <10000000>, <250000000>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>,
 		 <&clk IMX8MM_CLK_PCIE1_PHY>;
 	clock-names = "pcie", "pcie_aux", "pcie_bus";
 	pinctrl-names = "default";
@@ -649,6 +650,7 @@  &pcie0 {
 
 &pcie_phy {
 	clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+	clock-names = "ref";
 	fsl,clkreq-unsupported;
 	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
 	fsl,tx-deemph-gen1 = <0x2d>;