From patchwork Mon Sep 26 17:55:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 12989186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6062CC6FA90 for ; Mon, 26 Sep 2022 17:57:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PNZLvqcx50t1dYRGmt0drRRtESPg81NzuP0KGRxqDD0=; b=K5FXJwdPB5Zxf3 5/wuHRFFSTEFuG9fw3kxyQOCX6mxyKXNTTeDADf6N1KpkzO2usLsR/XPzuICRP8bfZIhSXh9A3P34 JR1UQyGZCx9hHNlq42TfOPeWEqKaIFYnlkcKrMiLbFs3iGt1P7JkCvbzElMPF0VQWrgV9p8LyyDof QvVHe7SxC6GeSYB1igIh5/DmfigswpzOEob+um76dpte7s6ezdthq9hRTI4b7YU7iOSt8ODdZnroM 2ZoboAkz5B0oGP89qjNGedZjE+EUTWtF1sbnDlGWL5rXz3JYPPGvFs60Z8KSDvmipDcv2EIws3fJ1 ty447zwCrSNiXTa8Cbiw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocsL2-006Aiu-C6; Mon, 26 Sep 2022 17:56:16 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocsKl-006ASo-9f for linux-arm-kernel@lists.infradead.org; Mon, 26 Sep 2022 17:56:00 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28QHtl5S109936; Mon, 26 Sep 2022 12:55:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1664214947; bh=ohT/Xt+gQdamRFphhGmgt8mEN9/4WnQBb8A+NOnxztw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AyIbIWyM+J9K9A0y6PRqWOgNLZkegbdQ3ZMgp12NdrmUl44cvVeDhGt+nqu/rjr5r aXwRRaxioKfGgtlbNDpSpaWch5TRh+urVKKpTl4eoewLtK804PQD+QQSrZATL4CTtX JmuEvZJiihlUeaLP9zAIkBFJ6EIe5i99XcqSND7A= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28QHtlSl061117 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 26 Sep 2022 12:55:47 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Mon, 26 Sep 2022 12:55:47 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Mon, 26 Sep 2022 12:55:47 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28QHtjnw037500; Mon, 26 Sep 2022 12:55:46 -0500 From: Matt Ranostay To: , , , , CC: , , , Matt Ranostay Subject: [PATCH v2 1/3] PCI: j721e: Add PCIe 4x lane selection support Date: Mon, 26 Sep 2022 10:55:36 -0700 Message-ID: <20220926175538.362018-2-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 In-Reply-To: <20220926175538.362018-1-mranostay@ti.com> References: <20220926175538.362018-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220926_105559_438953_E18A592A X-CRM114-Status: GOOD ( 12.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for setting of two-bit field that allows selection of 4x lane PCIe which was previously limited to only 2x lanes. Cc: Kishon Vijay Abraham I Signed-off-by: Matt Ranostay --- drivers/pci/controller/cadence/pci-j721e.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index a82f845cc4b5..d9b1527421c3 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -43,7 +43,6 @@ enum link_status { }; #define J721E_MODE_RC BIT(7) -#define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) #define GENERATION_SEL_MASK GENMASK(1, 0) @@ -207,11 +206,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, { struct device *dev = pcie->cdns_pcie->dev; u32 lanes = pcie->num_lanes; + u32 mask = GENMASK(8, 8); u32 val = 0; int ret; + if (lanes == 4) + mask = GENMASK(9, 8); + val = LANE_COUNT(lanes - 1); - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set link count\n");