From patchwork Tue Sep 27 02:56:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12989733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D51BEC07E9D for ; Tue, 27 Sep 2022 02:59:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9CL3S1uOYX7/LubLpPKi8b1zbsBYwjyj6+iebOofexs=; b=ha+cAa7i+LGjWx 0Cxm6a4kVLa7+LYtaX/aRAb4mCAwzA6NMQEV62/m1Elm8fanciYh3uiHpjI6xGQZLjjzcLGkG9MJm MRWJVyAxVFZC1KZE79xKoEV7jQPrFNjObVED83PUlZmnAjYzlCC2ntxKS/YVoGtTog/0IcKaCkKI4 Rb3texdRtcrQA9BlEqb2GJ9+yP9Fjj+4jAC00HZNHZLgyJyTBGawo9NpoZW2khTNvmdGVY+OIEGt8 MXjcY1nxJtKtmcNN6UwNFxE7RR66uVGl0Y4M5JZDvLP7W9irc5X6QCE0drB35JzhkRTufzaX91xu9 NutvEGiUW5ssH8vn0E1A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1od0mz-007zeB-9e; Tue, 27 Sep 2022 02:57:41 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1od0mt-007zd7-SN; Tue, 27 Sep 2022 02:57:37 +0000 X-UUID: 62b001864b3249888cd2cff0a94a313e-20220926 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=97xymXwMEE5zenhKfd2GRaKXBKHtYdXb8q1Jd9/1lY4=; b=X+AG0uDHjuYr8WHqO/1UAUYHtHT3hWVRHjcJy52y6FUjMsVfdEek9sERYfL4t87j69UwMtxrqSXcpngJG1HRP5jzMTOiymcn/x7p01Hh5dDy/K0QqkwAGZfOYmRgl6zn1rBegcadxZCqYQfsFM8aYWL0YWEnmUWwXLqrVrZqegQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:dc5f22fc-de54-4fcd-8e64-35479a41dfef,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:42c71c07-1cee-4c38-b21b-a45f9682fdc0,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 62b001864b3249888cd2cff0a94a313e-20220926 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 220022098; Mon, 26 Sep 2022 19:57:30 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 27 Sep 2022 10:56:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 27 Sep 2022 10:56:27 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Tinghan Shen CC: , , , , , Subject: [PATCH v3 10/11] remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout Date: Tue, 27 Sep 2022 10:56:05 +0800 Message-ID: <20220927025606.26673-11-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220927025606.26673-1-tinghan.shen@mediatek.com> References: <20220927025606.26673-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220926_195735_927033_8BB0DA81 X-CRM114-Status: GOOD ( 16.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The MT8195 SCP core 1 watchdog timeout needs to be handled in the SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout IRQ is wired on the same IRQ entry for core 0 watchdog timeout. MT8195 SCP has a watchdog status register to identify the watchdog timeout source when IRQ triggered. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 4 +++ drivers/remoteproc/mtk_scp.c | 44 ++++++++++++++++++++++++++++++++- 2 files changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index dcde25f8bbf9..6cd04ca9e681 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -55,6 +55,10 @@ #define MT8192_CORE0_WDT_IRQ 0x10030 #define MT8192_CORE0_WDT_CFG 0x10034 +#define MT8195_SYS_STATUS 0x4004 +#define MT8195_CORE0_WDT BIT(16) +#define MT8195_CORE1_WDT BIT(17) + #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) #define MT8195_CPU1_SRAM_PD 0x1084 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 0f1b587f8502..159f3c69cd69 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -222,6 +222,48 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + } else { + if (readl(scp->reg_base + MT8195_SYS_STATUS) & MT8195_CORE1_WDT) { + struct device_node *c1_np; + struct platform_device *c1_pdev; + struct mtk_scp *c1_scp; + + writel(1, scp->reg_base + MT8195_CORE1_WDT_IRQ); + + c1_np = of_get_compatible_child(scp->dev->of_node, + "mediatek,mt8195-scp-core"); + if (!c1_np) { + dev_err(scp->dev, "cannot find core 1 node\n"); + goto clear_irq; + } + + c1_pdev = of_find_device_by_node(c1_np); + of_node_put(c1_np); + if (!c1_pdev) { + dev_err(scp->dev, "cannot find core 1 pdev\n"); + goto clear_irq; + } + + c1_scp = platform_get_drvdata(c1_pdev); + scp_wdt_handler(c1_scp, scp_to_host); + } else { + writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); + scp_wdt_handler(scp, scp_to_host); + } + } + +clear_irq: + writel(scp_to_host, scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); +} + static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -1155,7 +1197,7 @@ static const struct mtk_scp_of_data mt8192_of_data = { static const struct mtk_scp_of_data mt8195_of_data = { .scp_clk_get = mt8195_scp_clk_get, .scp_before_load = mt8195_scp_before_load, - .scp_irq_handler = mt8192_scp_irq_handler, + .scp_irq_handler = mt8195_scp_irq_handler, .scp_reset_assert = mt8192_scp_reset_assert, .scp_reset_deassert = mt8192_scp_reset_deassert, .scp_stop = mt8195_scp_stop,