From patchwork Tue Sep 27 02:55:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12989809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9583BC32771 for ; Tue, 27 Sep 2022 03:18:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oaraMYVXXZ+mpIf0YTTQ7cQY8C9yxD99nvVaNtxeieE=; b=OanuUKv6ONxIoO WEdrZfiBw/fw5RqD4j+yyr/8NQr1qQBLYuP0j/El6yx0mkw3EAltUWz/MlJERhhOTlYkkTJ4JFQJ9 fN8b3giSmWMCXMmlnfymmrHP6KGwzjMZ5mg5+W/f/Q/zUqliRpKn5nyq1SAIXAfZ6wkpsGsLiWBKL L+aqfHWKr3lbNXGQvxNW5J6fkc9unmKCtJd2xjZ/pyWQxCOQVjTW6+Uu9gCEPI8DRQrrZYXq5mtti SE1rw+gUssL34i2bRLJvdT1t4tqNr0vs7AWRFVbrxm0uJbnxrsgEucgpNiyLe9FnzqyBv45hzMpQs 2MSprz3KzVhffOK8ELqQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1od15u-0083Py-1k; Tue, 27 Sep 2022 03:17:14 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1od15m-0083Mw-6s; Tue, 27 Sep 2022 03:17:09 +0000 X-UUID: 92f67857c1714b00b22fb5049d9067a8-20220926 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EnCltdT6Z6EH/J8fbqpmMgDX4Y07nMwnORWprAExDOA=; b=Rhnrz91+BeB+Ryi2/BhFcSSzivY+PT0t6PwKGYL3CjA0YSJH58K1A4XZbFvqHwdLddq0OJEWquXIxuOkhdezmVRDRDp3HverVEPa178lZtQuJroZm0CrVtR1hObe3/jnsQffjjGcS1lEnXntpyqs0D8UEZp/+Rhu1hq2Ke5LMuc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:90b0516f-3243-478d-8bd1-a9e2e4574bb5,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:877a2ba3-dc04-435c-b19b-71e131a5fc35,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 92f67857c1714b00b22fb5049d9067a8-20220926 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1306038186; Mon, 26 Sep 2022 20:17:00 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 27 Sep 2022 10:56:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 27 Sep 2022 10:56:25 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Tinghan Shen CC: , , , , , Subject: [PATCH v3 02/11] dt-bindings: remoteproc: mediatek: Support MT8195 dual-core SCP Date: Tue, 27 Sep 2022 10:55:57 +0800 Message-ID: <20220927025606.26673-3-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220927025606.26673-1-tinghan.shen@mediatek.com> References: <20220927025606.26673-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220926_201707_696489_DA3625C5 X-CRM114-Status: GOOD ( 17.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The MT8195 SCP is a dual-core RISC-V MCU. Extend the yaml file to describe the 2nd core as a subnode of the boot core. The configuration register is shared by MT8195 SCP core 0 and core 1. The core 1 can retrieve the information of configuration registers from parent node. Signed-off-by: Tinghan Shen --- .../bindings/remoteproc/mtk,scp.yaml | 97 ++++++++++++++++++- 1 file changed, 92 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 786bed897916..c012265be4eb 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -75,6 +75,83 @@ properties: required: - mediatek,rpmsg-name + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^scp-c[0-9]+@[a-f0-9]+$": + type: object + description: + The MediaTek SCP integrated to SoC might be a multi-core version. + The other cores are represented as child nodes of the boot core. + There are some integration differences for the IP like the usage of + address translator for translating SoC bus addresses into address space + for the processor. + + Each SCP core has own cache memory. The SRAM and L1TCM are shared by + cores. The power of cache, SRAM and L1TCM power should be enabled + before booting SCP cores. The size of cache, SRAM, and L1TCM are varied + on differnt SoCs. + + The SCP cores do not use an MMU, but has a set of registers to + control the translations between 32-bit CPU addresses into system bus + addresses. Cache and memory access settings are provided through a + Memory Protection Unit (MPU), programmable only from the SCP. + + properties: + compatible: + enum: + - mediatek,mt8195-scp-core + + reg: + description: The base address and size of SRAM. + maxItems: 1 + + reg-names: + const: sram + + interrupts: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + If present, name (or relative path) of the file within the + firmware search path containing the firmware image used when + initializing sub cores of multi-core SCP. + + memory-region: + maxItems: 1 + + cros-ec-rpmsg: + type: object + description: + This subnode represents the rpmsg device. The namesof the devices + are not important. The properties of this node are defined by the + individual bindings for the rpmsg devices. + + properties: + mediatek,rpmsg-name: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Contains the name for the rpmsg device. Used to match + the subnode to rpmsg device announced by SCP. + + required: + - mediatek,rpmsg-name + + required: + - compatible + - reg + - reg-names + + additionalProperties: false + required: - compatible - reg @@ -110,16 +187,26 @@ additionalProperties: false examples: - | - #include - scp@10500000 { - compatible = "mediatek,mt8192-scp"; + compatible = "mediatek,mt8195-scp"; reg = <0x10500000 0x80000>, <0x10700000 0x8000>, <0x10720000 0xe0000>; reg-names = "sram", "cfg", "l1tcm"; - clocks = <&infracfg CLK_INFRA_SCPSYS>; - clock-names = "main"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x105a0000 0x105a0000 0x20000>; + + scp-c1@105a0000 { + compatible = "mediatek,mt8195-scp-core"; + reg = <0x105a0000 0x20000>; + reg-names = "sram"; + + cros-ec-rpmsg { + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; + }; cros-ec-rpmsg { mediatek,rpmsg-name = "cros-ec-rpmsg";