@@ -26,9 +26,6 @@
/* Number of channels per memory controller */
#define SNPS_EDAC_NR_CHANS 1
-/* Granularity of reported error in bytes */
-#define SNPS_EDAC_ERR_GRAIN 1
-
#define SNPS_EDAC_MSG_SIZE 256
#define SNPS_EDAC_MOD_STRING "snps_edac"
@@ -733,9 +730,12 @@ static void snps_init_csrows(struct mem_ctl_info *mci)
struct snps_edac_priv *priv = mci->pvt_info;
struct csrow_info *csi;
struct dimm_info *dimm;
- u32 size, row;
+ u32 size, row, width;
int j;
+ /* Actual SDRAM-word width for which ECC is calculated */
+ width = 1U << (priv->info.dq_width - priv->info.dq_mode);
+
for (row = 0; row < mci->nr_csrows; row++) {
csi = mci->csrows[row];
size = snps_get_memsize();
@@ -745,7 +745,7 @@ static void snps_init_csrows(struct mem_ctl_info *mci)
dimm->edac_mode = EDAC_SECDED;
dimm->mtype = priv->info.sdram_mode;
dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
- dimm->grain = SNPS_EDAC_ERR_GRAIN;
+ dimm->grain = width;
dimm->dtype = priv->info.dev_cfg;
}
}
It was wrong to set the DIMM errors grain parameter to just 1 byte because DW uMCTL2 DDRC calculates ECC for each SDRAM word and passes it as an additional byte of data to the memory chips. SDRAM word is the actual DQ-bus width determined by the DQ-width set during the IP-core synthesize and the DQ-bus mode (part of the DQ-bus actually used to get data from the memory chips) selected during the DDR controller initial setup procedure. Thus let's set the MCI DIMMs grain based on these parameters determined during the DW uMCTL2 DDRC config getting procedure. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/edac/synopsys_edac.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)