| Message ID | 20220929234121.13955-3-Sergey.Semin@baikalelectronics.ru (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | EDAC/synopsys: Add generic resources and Baikal-T1 support | expand |
On Fri, 30 Sep 2022 02:41:10 +0300, Serge Semin wrote: > Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a > with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There > are individual IRQs for each ECC and DFI events. The dedicated scrubber > clock source is absent since it's fully synchronous to the core clock. > In addition to that the DFI-DDR PHY CSRs can be accessed via a separate > registers space. > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > Reviewed-by: Rob Herring <robh@kernel.org> > > --- > > Changelog v2: > - Keep the alphabetically ordered compatible strings list. (@Krzysztof) > - Fix grammar nitpicks in the patch log. (@Krzysztof) > - Drop the PHY CSR region. (@Rob) > - Move the device bindings to the separate DT-schema. > --- > .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-common.yaml Error: Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.example.dts:41.30-31 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [scripts/Makefile.lib:384: Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1420: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On 03/10/2022 15:24, Rob Herring wrote: > On Fri, 30 Sep 2022 02:41:10 +0300, Serge Semin wrote: >> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a >> with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There >> are individual IRQs for each ECC and DFI events. The dedicated scrubber >> clock source is absent since it's fully synchronous to the core clock. >> In addition to that the DFI-DDR PHY CSRs can be accessed via a separate >> registers space. >> >> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> >> Reviewed-by: Rob Herring <robh@kernel.org> >> >> --- >> >> Changelog v2: >> - Keep the alphabetically ordered compatible strings list. (@Krzysztof) >> - Fix grammar nitpicks in the patch log. (@Krzysztof) >> - Drop the PHY CSR region. (@Rob) >> - Move the device bindings to the separate DT-schema. >> --- >> .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ >> 1 file changed, 91 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > ./Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-common.yaml This is result of patch #1 failing to apply: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20220929234121.13955-2-Sergey.Semin@baikalelectronics.ru/ The bindings look ok, but anyway it is a merge window now. Best regards, Krzysztof
On Wed, Oct 05, 2022 at 04:59:52PM +0200, Krzysztof Kozlowski wrote: > On 03/10/2022 15:24, Rob Herring wrote: > > On Fri, 30 Sep 2022 02:41:10 +0300, Serge Semin wrote: > >> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a > >> with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There > >> are individual IRQs for each ECC and DFI events. The dedicated scrubber > >> clock source is absent since it's fully synchronous to the core clock. > >> In addition to that the DFI-DDR PHY CSRs can be accessed via a separate > >> registers space. > >> > >> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > >> Reviewed-by: Rob Herring <robh@kernel.org> > >> > >> --- > >> > >> Changelog v2: > >> - Keep the alphabetically ordered compatible strings list. (@Krzysztof) > >> - Fix grammar nitpicks in the patch log. (@Krzysztof) > >> - Drop the PHY CSR region. (@Rob) > >> - Move the device bindings to the separate DT-schema. > >> --- > >> .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ > >> 1 file changed, 91 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml > >> > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > > > yamllint warnings/errors: > > > > dtschema/dtc warnings/errors: > > ./Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-common.yaml > > This is result of patch #1 failing to apply: > > https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20220929234121.13955-2-Sergey.Semin@baikalelectronics.ru/ I couldn't parse the patch-applied log < error: sha1 information is lacking or useless (Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml). < error: could not build fake ancestor < hint: Use 'git am --show-current-patch=diff' to see the failed patch What does it mean? -Sergey > > The bindings look ok, but anyway it is a merge window now. > > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml new file mode 100644 index 000000000000..80353a0a676f --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 DDR Controller + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: + Baikal-T1 DDRC is based on the DW uMCTL2 DDRC IP-core v2.51a with DDR2 + and DDR3 protocol capability, 32-bit data bus + 8-bit ECC + up to 2 + SDRAM ranks. There are individual IRQs for each ECC and DFI events. + The dedicated scrubber clock source is absent since it's fully + synchronous to the core clock. + +allOf: + - $ref: /schemas/memory-controllers/snps,dw-umctl2-common.yaml# + +properties: + compatible: + const: baikal,bt1-ddrc + + reg: + maxItems: 1 + + interrupts: + maxItems: 4 + + interrupt-names: + items: + - const: dfi_e + - const: ecc_ce + - const: ecc_ue + - const: ecc_sbr + + clocks: + maxItems: 3 + + clock-names: + items: + - const: pclk + - const: aclk + - const: core + + resets: + maxItems: 2 + + reset-names: + items: + - const: arst + - const: core + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/clock/bt1-ccu.h> + #include <dt-bindings/reset/bt1-ccu.h> + + memory-controller@1f042000 { + compatible = "baikal,bt1-ddrc"; + reg = <0x1f042000 0x1000>; + + interrupts = <GIC_SHARED 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 99 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dfi_e", "ecc_ce", "ecc_ue", "ecc_sbr"; + + clocks = <&ccu_sys CCU_SYS_APB_CLK>, + <&ccu_axi CCU_AXI_DDR_CLK>, + <&ccu_pll CCU_DDR_PLL>; + clock-names = "pclk", "aclk", "core"; + + resets = <&ccu_axi CCU_AXI_DDR_RST>, + <&ccu_sys CCU_SYS_DDR_INIT_RST>; + reset-names = "arst", "core"; + }; +...