From patchwork Fri Sep 30 14:01:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 12995475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2BA3FC433FE for ; Fri, 30 Sep 2022 14:07:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OvIiIv/aVob395rTqaWi9ZeAALQGJIHlyWC/wQeArTE=; b=fWBlbBpFbVS/95 hMjiMhj4A3tHY72BWEitZVlhJuO8XSkiQWo0afmvemAiKlzQrIA+Da+CxxbD7Ru21rZ/LrtK1/hpD AC1TnbHtjnq5juDXPvfQljXTTO4v0sJ9MWtkvPhCAMaWW8qJFYfzWDvkm8GcWDc+zYdoj4Hzjsfm8 TBuUoREH3SDjbNdwwMpAQIEFgLvdUT++oCD4SPvvBgA/homJvEjzqHMVZVqASdTPxP4Qz28HVNAo6 yLlGRb5iyp3bgFr5wk5mLlCtAy96w+4JdqTiy/3CJNoXvh+Y+lzRIzpv17BFOoaKjULp+LaA+ZwOo nauvHfPetKuGwZvdBd3g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oeGeX-009Yo5-Gq; Fri, 30 Sep 2022 14:06:10 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oeGb1-009WwY-9J for linux-arm-kernel@lists.infradead.org; Fri, 30 Sep 2022 14:02:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E42BB13D5; Fri, 30 Sep 2022 07:02:36 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A99A63F792; Fri, 30 Sep 2022 07:02:29 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Mark Brown , james.morse@arm.com Subject: [RFC PATCH 10/38] arm64/sysreg: Standardise naming for ID_PFR2_EL1 Date: Fri, 30 Sep 2022 15:01:43 +0100 Message-Id: <20220930140211.3215348-11-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220930140211.3215348-1-james.morse@arm.com> References: <20220930140211.3215348-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220930_070231_396675_9367E6DC X-CRM114-Status: GOOD ( 11.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To convert the 32bit id registers to use the sysreg generation, they must first have a regular pattern, to match the symbols the script generates. Ensure symbols for the ID_PFR2_EL1 register have an _EL1 suffix. No functional change. Signed-off-by: James Morse --- arch/arm64/include/asm/sysreg.h | 4 ++-- arch/arm64/kernel/cpufeature.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index f50b0d24c545..ff9814290f43 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -768,8 +768,8 @@ #define ID_DFR0_COPSDBG_SHIFT 4 #define ID_DFR0_COPDBG_SHIFT 0 -#define ID_PFR2_SSBS_SHIFT 4 -#define ID_PFR2_CSV3_SHIFT 0 +#define ID_PFR2_EL1_SSBS_SHIFT 4 +#define ID_PFR2_EL1_CSV3_SHIFT 0 #define MVFR0_FPROUND_SHIFT 28 #define MVFR0_FPSHVEC_SHIFT 24 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 982d670ec566..7e3bbd2e69e3 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -536,8 +536,8 @@ static const struct arm64_ftr_bits ftr_id_pfr1[] = { }; static const struct arm64_ftr_bits ftr_id_pfr2[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), ARM64_FTR_END, };