From patchwork Fri Sep 30 14:02:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 12995526 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7BD4CC433FE for ; Fri, 30 Sep 2022 14:20:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=X1kreTgvREPZQ+zycO2G1ozTN2h4+XmFiIiprpZOZNM=; b=1Pe7ZrWWvHxI1i gTuHZH8O3qMDukUGdFWTH9ciZfiIlBiyjUFeCfzKt8bxRXjJLKZ7+K5O/meMwjeV+RvJgHdm5DC/b jxWxHAFWtzWGc0CWYu7XzPmOSFPAb7PTzh3SAvc69ucHQb6fURg15YyX3wVvnLfHb8qWg8oLAnkTH uBi+sA/a290q9kHlTyuIPVDFApUSN8WJxOpmugj9gclei0fFsBwvMWXuKm79btPEpnft9q6GtWcWu ErBHB/Xk7flT/lS3bo89AyPP0nye4JB0w7ZlM3IL3K8ettuaZia66mTo0oVfxBChqUN693FNeo8FU aSPMOC+BFkQtp5/HtMQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oeGra-009gFb-7z; Fri, 30 Sep 2022 14:19:38 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oeGbF-009WwY-Ds for linux-arm-kernel@lists.infradead.org; Fri, 30 Sep 2022 14:02:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 74D1113D5; Fri, 30 Sep 2022 07:02:51 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3A4603F792; Fri, 30 Sep 2022 07:02:44 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Mark Brown , james.morse@arm.com Subject: [RFC PATCH 29/38] arm64/sysreg: Convert ID_PFR0_EL1 to automatic generation Date: Fri, 30 Sep 2022 15:02:02 +0100 Message-Id: <20220930140211.3215348-30-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220930140211.3215348-1-james.morse@arm.com> References: <20220930140211.3215348-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220930_070245_543254_49A59C35 X-CRM114-Status: GOOD ( 10.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert ID_PFR0_EL1 to be automatically generated as per DDI04187H.a, no functional changes. Signed-off-by: James Morse --- arch/arm64/include/asm/sysreg.h | 8 ------- arch/arm64/tools/sysreg | 41 +++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 4e9cb26bd60a..83f46c130fb3 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -165,7 +165,6 @@ #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) -#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) @@ -688,13 +687,6 @@ #define ID_MMFR5_EL1_ETS_SHIFT 0 -#define ID_PFR0_EL1_DIT_SHIFT 24 -#define ID_PFR0_EL1_CSV2_SHIFT 16 -#define ID_PFR0_EL1_State3_SHIFT 12 -#define ID_PFR0_EL1_State2_SHIFT 8 -#define ID_PFR0_EL1_State1_SHIFT 4 -#define ID_PFR0_EL1_State0_SHIFT 0 - #define ID_DFR0_EL1_PerfMon_SHIFT 24 #define ID_DFR0_EL1_MProfDbg_SHIFT 20 #define ID_DFR0_EL1_MMapTrc_SHIFT 16 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index eba4bf0d1479..9403549b1458 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -46,6 +46,47 @@ # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration # item ACCDATA) though it may be more taseful to do something else. +Sysreg ID_PFR0_EL1 3 0 0 1 0 +Res0 63:32 +Enum 31:28 RAS + 0b0000 NI + 0b0001 RAS + 0b0010 RASv1p1 +EndEnum +Enum 27:24 DIT + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 AMU + 0b0000 NI + 0b0001 AMUv1 + 0b0010 AMUv1p1 +EndEnum +Enum 19:16 CSV2 + 0b0000 NI + 0b0001 CSV2p1 + 0b0010 CSV2p2 +EndEnum +Enum 15:12 State3 + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 State2 + 0b0000 NI + 0b0001 NO_CV + 0b0010 CV +EndEnum +Enum 7:4 State1 + 0b0000 NI + 0b0001 THUMB + 0b0010 THUMB2 +EndEnum +Enum 3:0 State0 + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_MMFR0_EL1 3 0 0 1 4 Res0 63:32 Enum 31:28 InnerShr