From patchwork Fri Sep 30 14:02:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 12995556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67F97C433FE for ; Fri, 30 Sep 2022 14:26:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LpWpo3FF/OFNidVZJxUgnPcasEzHa22gaEZYCXAlhJo=; b=xbv8jFhtxNEOFw CFolpDPdHl06ABFhieEOIN1nejfE7clKvW06J3D5a9AxyvgOEBARfsX9hiP9wA4QIxIhHw2iuFiLA U66ImfnePyew5pHTXNOYy+N0+KvuxNaLtyhP3gCVMvtJCcyKUqVlQMx5RPQWieoZ6yFwgt5wYQnDj /ivK9PE2EjyoueS6nTX+XFpupIoPdSKsKpG6fq0uaQ933plJbdpQ/46rXbr+UnjL+oRz68m+uM03A y/qhxvuO+C3IJjAmT+7y0Lzi+oXAXrjrL/z8mR90jPS3V55n22JWIp5Di9TeEO+0NPGzxZvbknHpK m+EE1IauG8JYA/rOSiiA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oeGx2-009jok-HI; Fri, 30 Sep 2022 14:25:16 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oeGbI-009XBJ-9L for linux-arm-kernel@lists.infradead.org; Fri, 30 Sep 2022 14:02:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 839B7244C; Fri, 30 Sep 2022 07:02:54 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 493B03F792; Fri, 30 Sep 2022 07:02:47 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Mark Brown , james.morse@arm.com Subject: [RFC PATCH 33/38] arm64/sysreg: Convert MVFR1_EL1 to automatic generation Date: Fri, 30 Sep 2022 15:02:06 +0100 Message-Id: <20220930140211.3215348-34-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220930140211.3215348-1-james.morse@arm.com> References: <20220930140211.3215348-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220930_070248_403523_AD89F0EB X-CRM114-Status: UNSURE ( 8.91 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert MVFR1_EL1 to be automatically generated as per DDI04187H.a, no functional changes. Signed-off-by: James Morse Reviewed-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 10 --------- arch/arm64/tools/sysreg | 39 +++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index d3ff4a1aa805..055beb7b1bcc 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -170,7 +170,6 @@ #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) -#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) @@ -692,15 +691,6 @@ #define ID_DFR0_EL1_CopSDbg_SHIFT 4 #define ID_DFR0_EL1_CopDbg_SHIFT 0 -#define MVFR1_EL1_SIMDFMAC_SHIFT 28 -#define MVFR1_EL1_FPHP_SHIFT 24 -#define MVFR1_EL1_SIMDHP_SHIFT 20 -#define MVFR1_EL1_SIMDSP_SHIFT 16 -#define MVFR1_EL1_SIMDInt_SHIFT 12 -#define MVFR1_EL1_SIMDLS_SHIFT 8 -#define MVFR1_EL1_FPDNaN_SHIFT 4 -#define MVFR1_EL1_FPFtZ_SHIFT 0 - #if defined(CONFIG_ARM64_4K_PAGES) #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index f69bdb1d1ee4..c4d20f12c277 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -644,6 +644,45 @@ Enum 3:0 SIMDReg EndEnum EndSysreg +Sysreg MVFR1_EL1 3 0 0 3 1 +Res0 63:32 +Enum 31:28 SIMDFMAC + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 27:24 FPHP + 0b0000 NI + 0b0001 FPHP + 0b0010 FPHP_CONV + 0b0011 FP16 +EndEnum +Enum 23:20 SIMDHP + 0b0000 NI + 0b0001 SIMDHP + 0b0001 SIMDHP_FLOAT +EndEnum +Enum 19:16 SIMDSP + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 SIMDInt + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 SIMDLS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 7:4 FPDNaN + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 3:0 FPFtZ + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_PFR2_EL1 3 0 0 3 4 Res0 63:12 Enum 11:8 RAS_frac