From patchwork Wed Oct 12 14:22:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olivier Moysan X-Patchwork-Id: 13005105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9928EC433FE for ; Wed, 12 Oct 2022 14:25:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=j2IiwcRY3AKZQH2toGLiCskafoyxj8gOpqL8jiX9ePg=; b=0SbtJn+qDHEsV+ wCjWUbBDdt0xmatyEJ7dA4z2TYPQZUNra3AX3EQWXF1l9JBfFRptTeyuEBaJ1bfioLOpuOqaU/A3h 9QSgqoxSyJRS1aMAgg2V7wPSsbV0fUAuiFG3fZhrTU1DRut4SWayA2567UsLnpT5PPBLCsN0yMvOk nphFV209SizM+JU/68qXDVhkMk8+eziDQRxA59I5Tz84kg824J15XAis+5Br9230nZqrzqfe3s1TH Bq96SPml9AemzdaGR4L/28Vsd1gGmp/wng2ayw5Lpo2P+OC8yhTOg7J+GKLckjeKLrzyLgSP70vX4 n2SIZX5d4AlLBoI93/lg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oicek-008LwG-Lm; Wed, 12 Oct 2022 14:24:22 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oiced-008LsX-Ux for linux-arm-kernel@lists.infradead.org; Wed, 12 Oct 2022 14:24:17 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29CAd0Ja013870; Wed, 12 Oct 2022 16:24:11 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=94kx+zVIECZQcMvyw3cdcKGJUt8Yypqp4RBETTZpPps=; b=jr6Bu//nrq5TUN3k3dEi9FXP++8OXK5EuaYbrAtyKGEB1Ye8ZXN9140+1D3M4ZD2d/ss tCAjb0v+BSFWiiI3rp59XsxRbVOoyn0lrJrQQovU01O8YW+IHFfGXvvxINSCQHUkT3vx +fYKoZEn7jk7lJv/g3f3ymHPpK67GEozrvtcKeTqPfDS8DIBVbiu0ir2TCsg6pvCrP1J u1BomWC6TEaKZSf68cYpHCIZ/XpFLmRol4hRGhg1JgRqWl/4nfvdMml0hFvoi2NJWRjj CYHQyRc4nuRGo2VeA/2pfihw9oFE59XD5Yn9bjQFldhq05o6M+9LuoqMWm2Gg3r+FZZj DA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3k31gq3kj6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Oct 2022 16:24:11 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 25AB710003B; Wed, 12 Oct 2022 16:24:08 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 20A0022FA2A; Wed, 12 Oct 2022 16:24:08 +0200 (CEST) Received: from localhost (10.75.127.118) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2375.31; Wed, 12 Oct 2022 16:24:07 +0200 From: Olivier Moysan To: Rob Herring , Alexandre Torgue , Andy Shevchenko , Fabrice Gasnier , Jonathan Cameron , Lars-Peter Clausen , Maxime Coquelin , Olivier Moysan CC: , , , , Subject: [PATCH v4 5/8] ARM: dts: stm32: add adc support to stm32mp13 Date: Wed, 12 Oct 2022 16:22:02 +0200 Message-ID: <20221012142205.13041-6-olivier.moysan@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221012142205.13041-1-olivier.moysan@foss.st.com> References: <20221012142205.13041-1-olivier.moysan@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.118] X-ClientProxiedBy: GPXDAG2NODE6.st.com (10.75.127.70) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-12_07,2022-10-12_01,2022-06-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221012_072416_293757_50851FF7 X-CRM114-Status: GOOD ( 16.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add ADC1 and ADC2 support to STM32MP13 SoC family. The STM32MP131 provides only ADC2, while other STM32MP13 SoCs provide both ADC1 and ADC2. Internal channels support limitations: - VREFINT internal channel requires calibration data from OTP memory. The nvmem properties used to access OTP are not defined for time being, as OTP support is not yet enabled. - VBAT internal channel is not defined by default in SoC DT, and has be defined in board DT when needed, instead. This avoids unwanted current consumption on battery, when ADC conversions are performed on any other channels. Signed-off-by: Olivier Moysan Reviewed-by: Fabrice Gasnier --- arch/arm/boot/dts/stm32mp131.dtsi | 43 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32mp133.dtsi | 31 ++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index dd35a607073d..0b85e7744db5 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -313,6 +313,49 @@ i2c5: i2c@4c006000 { status = "disabled"; }; + adc_2: adc@48004000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48004000 0x400>; + interrupts = ; + clocks = <&rcc ADC2>, <&rcc ADC2_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; + dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + channel@16 { + reg = <16>; + label = "vddcpu"; + }; + channel@17 { + reg = <17>; + label = "vddq_ddr"; + }; + }; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp13-rcc", "syscon"; reg = <0x50000000 0x1000>; diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi index 531c263c9f46..df451c3c2a26 100644 --- a/arch/arm/boot/dts/stm32mp133.dtsi +++ b/arch/arm/boot/dts/stm32mp133.dtsi @@ -33,5 +33,36 @@ m_can2: can@4400f000 { bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; + + adc_1: adc@48003000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48003000 0x400>; + interrupts = ; + clocks = <&rcc ADC1>, <&rcc ADC1_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@18 { + reg = <18>; + label = "vrefint"; + }; + }; + }; }; };