| Message ID | 20221017070858.13902-4-tinghan.shen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add driver nodes for MT8195 SoC | expand |
On 17/10/2022 03:08, Tinghan Shen wrote: > Add venc node for mt8195 SoC. > > Signed-off-by: Irui Wang <irui.wang@mediatek.com> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 903e92d6156f..7cf2f7ef4ec6 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -2163,6 +2163,30 @@ > power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; > }; > > + venc: venc@1a020000 { I think you called this video-codec in other patches... Would be great if you (you as folks working on Mediatek from Mediatek) keep patches consistent... > + compatible = "mediatek,mt8195-vcodec-enc"; > + reg = <0 0x1a020000 0 0x10000>; Best regards, Krzysztof
Il 17/10/22 09:08, Tinghan Shen ha scritto: > Add venc node for mt8195 SoC. > > Signed-off-by: Irui Wang <irui.wang@mediatek.com> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 903e92d6156f..7cf2f7ef4ec6 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -2163,6 +2163,30 @@ > power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; > }; > > + venc: venc@1a020000 { As Krzysztof also said, this is video-codec@1a020000. Also, there's one more thing... MT8195 has two video encoder cores, but this node is only for the first one. There's a second instance at 0x1b020000: please add it. Regards, Angelo
On Wed, 2022-10-19 at 10:51 +0200, AngeloGioacchino Del Regno wrote: > Il 17/10/22 09:08, Tinghan Shen ha scritto: > > Add venc node for mt8195 SoC. > > > > Signed-off-by: Irui Wang <irui.wang@mediatek.com> > > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> > > --- > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 > > ++++++++++++++++++++++++ > > 1 file changed, 24 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > index 903e92d6156f..7cf2f7ef4ec6 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > @@ -2163,6 +2163,30 @@ > > power-domains = <&spm > > MT8195_POWER_DOMAIN_VENC>; > > }; > > > > + venc: venc@1a020000 { > > As Krzysztof also said, this is video-codec@1a020000. > > Also, there's one more thing... MT8195 has two video encoder cores, > but this > node is only for the first one. There's a second instance at > 0x1b020000: please > add it. Dear Angelo, The second video encoder core 0x1b020000 is not ready in driver, there is only one core 0x1a020000 used, so we don't need add it in current patch now. Thanks Best Regards > > Regards, > Angelo >
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 903e92d6156f..7cf2f7ef4ec6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2163,6 +2163,30 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; + venc: venc@1a020000 { + compatible = "mediatek,mt8195-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,scp = <&scp>; + clocks = <&vencsys CLK_VENC_VENC>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + vencsys_core1: clock-controller@1b000000 { compatible = "mediatek,mt8195-vencsys_core1"; reg = <0 0x1b000000 0 0x1000>;