From patchwork Mon Oct 17 08:12:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfeng Ye X-Patchwork-Id: 13008291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7974EC433FE for ; Mon, 17 Oct 2022 08:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7g78Q5seaQBiy3LzhNWRYWRhyOCIbAsSNekrX+A0Kx4=; b=uHzwiq88dPi5SN OjABZqN0t/b+p7a4XTXMENpZ91GvNY1YqXluKb6jz6EcAgqPEz5hNFtKsgLtiWhI0FbbEPjiu7nje zdZfNpg+wea1pdc3L8ClvddM853N0mBX6vxjXDVuscsEjE4uq1IuujR+UBYm02ufkFsaQ7RFfaWBd l+4sXqAu0FDCdKqPA0+wXuYaiTRBGU4KRRvZblNlLpjk07EQu8XAOBjrAuXKrUOd97KZ7D+cP4dnB rLsNiZ4LB7Vq2O2rMUlYtjuwjiCBfKwckAkqLD3oWPDt5Js7uBGo0rkr6tAoL4gRnvfD5K7xqwZdM Sar+1BEkdaFwvlV2cZKw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1okLGB-008zUj-CO; Mon, 17 Oct 2022 08:14:07 +0000 Received: from szxga08-in.huawei.com ([45.249.212.255]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1okLFi-008z5G-RM for linux-arm-kernel@lists.infradead.org; Mon, 17 Oct 2022 08:13:41 +0000 Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4MrV4h2cfnz1P7SM; Mon, 17 Oct 2022 16:08:52 +0800 (CST) Received: from huawei.com (10.44.134.232) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 17 Oct 2022 16:13:03 +0800 From: y00318929 To: , , , , , Subject: [PATCH 1/5] arm64: mm: Define asid_bitmap structure for pinned_asid Date: Mon, 17 Oct 2022 16:12:54 +0800 Message-ID: <20221017081258.3678830-2-yeyunfeng@huawei.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221017081258.3678830-1-yeyunfeng@huawei.com> References: <20221017081258.3678830-1-yeyunfeng@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.44.134.232] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221017_011339_299928_73788F77 X-CRM114-Status: GOOD ( 13.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yunfeng Ye It is clearer to use the asid_bitmap structure for pinned_sid, and we will use it for isolated asid later. No functional change. Signed-off-by: Yunfeng Ye --- arch/arm64/mm/context.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index e1e0dca01839..8549b5f30352 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -17,6 +17,12 @@ #include #include +struct asid_bitmap { + unsigned long *map; + unsigned long nr; + unsigned long max; +}; + static u32 asid_bits; static DEFINE_RAW_SPINLOCK(cpu_asid_lock); @@ -27,9 +33,7 @@ static DEFINE_PER_CPU(atomic64_t, active_asids); static DEFINE_PER_CPU(u64, reserved_asids); static cpumask_t tlb_flush_pending; -static unsigned long max_pinned_asids; -static unsigned long nr_pinned_asids; -static unsigned long *pinned_asid_map; +static struct asid_bitmap pinned_asid; #define ASID_MASK (~GENMASK(asid_bits - 1, 0)) #define ASID_FIRST_VERSION (1UL << asid_bits) @@ -90,8 +94,8 @@ static void set_kpti_asid_bits(unsigned long *map) static void set_reserved_asid_bits(void) { - if (pinned_asid_map) - bitmap_copy(asid_map, pinned_asid_map, NUM_USER_ASIDS); + if (pinned_asid.map) + bitmap_copy(asid_map, pinned_asid.map, NUM_USER_ASIDS); else if (arm64_kernel_unmapped_at_el0()) set_kpti_asid_bits(asid_map); else @@ -275,7 +279,7 @@ unsigned long arm64_mm_context_get(struct mm_struct *mm) unsigned long flags; u64 asid; - if (!pinned_asid_map) + if (!pinned_asid.map) return 0; raw_spin_lock_irqsave(&cpu_asid_lock, flags); @@ -285,7 +289,7 @@ unsigned long arm64_mm_context_get(struct mm_struct *mm) if (refcount_inc_not_zero(&mm->context.pinned)) goto out_unlock; - if (nr_pinned_asids >= max_pinned_asids) { + if (pinned_asid.nr >= pinned_asid.max) { asid = 0; goto out_unlock; } @@ -299,8 +303,8 @@ unsigned long arm64_mm_context_get(struct mm_struct *mm) atomic64_set(&mm->context.id, asid); } - nr_pinned_asids++; - __set_bit(ctxid2asid(asid), pinned_asid_map); + pinned_asid.nr++; + __set_bit(ctxid2asid(asid), pinned_asid.map); refcount_set(&mm->context.pinned, 1); out_unlock: @@ -321,14 +325,14 @@ void arm64_mm_context_put(struct mm_struct *mm) unsigned long flags; u64 asid = atomic64_read(&mm->context.id); - if (!pinned_asid_map) + if (!pinned_asid.map) return; raw_spin_lock_irqsave(&cpu_asid_lock, flags); if (refcount_dec_and_test(&mm->context.pinned)) { - __clear_bit(ctxid2asid(asid), pinned_asid_map); - nr_pinned_asids--; + __clear_bit(ctxid2asid(asid), pinned_asid.map); + pinned_asid.nr--; } raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); @@ -377,8 +381,8 @@ static int asids_update_limit(void) if (arm64_kernel_unmapped_at_el0()) { num_available_asids /= 2; - if (pinned_asid_map) - set_kpti_asid_bits(pinned_asid_map); + if (pinned_asid.map) + set_kpti_asid_bits(pinned_asid.map); } /* * Expect allocation after rollover to fail if we don't have at least @@ -393,7 +397,7 @@ static int asids_update_limit(void) * even if all CPUs have a reserved ASID and the maximum number of ASIDs * are pinned, there still is at least one empty slot in the ASID map. */ - max_pinned_asids = num_available_asids - num_possible_cpus() - 2; + pinned_asid.max = num_available_asids - num_possible_cpus() - 2; return 0; } arch_initcall(asids_update_limit); @@ -407,8 +411,8 @@ static int asids_init(void) panic("Failed to allocate bitmap for %lu ASIDs\n", NUM_USER_ASIDS); - pinned_asid_map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); - nr_pinned_asids = 0; + pinned_asid.map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); + pinned_asid.nr = 0; /* * We cannot call set_reserved_asid_bits() here because CPU