diff mbox series

[05/15] arm64: dts: imx8mp-evk: enable uart1/3 ports

Message ID 20221020095934.1659449-6-peng.fan@oss.nxp.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: imx8m-evk: misc dts update | expand

Commit Message

Peng Fan (OSS) Oct. 20, 2022, 9:59 a.m. UTC 
From: Peng Fan <peng.fan@nxp.com>

Enable uart1/3 ports for evk board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
 1 file changed, 36 insertions(+)

Comments

Marco Felsch Oct. 20, 2022, 11:07 a.m. UTC | #1 
Hi Peng,

On 22-10-20, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Enable uart1/3 ports for evk board.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index 2e29bb3c041c..366f709f8790 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -428,6 +428,15 @@ &snvs_pwrkey {
>  	status = "okay";
>  };
>  
> +&uart1 { /* BT */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;

I'm curious, what is the default parent and why is this wrong? For the
already exisiting uart2 we don't do that. Same applies for uart3.

Regards,
  Marco


> +	fsl,uart-has-rtscts;
> +	status = "okay";
> +};
> +
>  &uart2 {
>  	/* console */
>  	pinctrl-names = "default";
> @@ -450,6 +459,15 @@ &usb_dwc3_1 {
>  	status = "okay";
>  };
>  
> +&uart3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart3>;
> +	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
> +	fsl,uart-has-rtscts;
> +	status = "okay";
> +};
> +
>  &usdhc2 {
>  	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
>  	assigned-clock-rates = <400000000>;
> @@ -625,6 +643,15 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
>  		>;
>  	};
>  
> +	pinctrl_uart1: uart1grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
> +			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
> +			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140
> +			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140
> +		>;
> +	};
> +
>  	pinctrl_uart2: uart2grp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
> @@ -638,6 +665,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x10
>  		>;
>  	};
>  
> +	pinctrl_uart3: uart3grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140
> +			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140
> +			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x140
> +			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
> +		>;
> +	};
> +
>  	pinctrl_usdhc2: usdhc2grp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
> -- 
> 2.37.1
> 
> 
>
Peng Fan (OSS) Oct. 21, 2022, 8:55 a.m. UTC | #2 
Hi Marco,

On 10/20/2022 7:07 PM, Marco Felsch wrote:
> Hi Peng,
> 
> On 22-10-20, Peng Fan (OSS) wrote:
>> From: Peng Fan <peng.fan@nxp.com>
>>
>> Enable uart1/3 ports for evk board.
>>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>   arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
>>   1 file changed, 36 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
>> index 2e29bb3c041c..366f709f8790 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
>> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
>> @@ -428,6 +428,15 @@ &snvs_pwrkey {
>>   	status = "okay";
>>   };
>>   
>> +&uart1 { /* BT */
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart1>;
>> +	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
>> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
> 
> I'm curious, what is the default parent and why is this wrong? For the
> already exisiting uart2 we don't do that. Same applies for uart3.

The default parent is OSC_24M. The uart2 is for console, so 24M is ok.
As I recall, we met issue 24M not able to get higher baudrate.


Regards,
Peng.
> 
> Regards,
>    Marco
> 
> 
>> +	fsl,uart-has-rtscts;
>> +	status = "okay";
>> +};
>> +
>>   &uart2 {
>>   	/* console */
>>   	pinctrl-names = "default";
>> @@ -450,6 +459,15 @@ &usb_dwc3_1 {
>>   	status = "okay";
>>   };
>>   
>> +&uart3 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart3>;
>> +	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
>> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
>> +	fsl,uart-has-rtscts;
>> +	status = "okay";
>> +};
>> +
>>   &usdhc2 {
>>   	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
>>   	assigned-clock-rates = <400000000>;
>> @@ -625,6 +643,15 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
>>   		>;
>>   	};
>>   
>> +	pinctrl_uart1: uart1grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
>> +			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
>> +			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140
>> +			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140
>> +		>;
>> +	};
>> +
>>   	pinctrl_uart2: uart2grp {
>>   		fsl,pins = <
>>   			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
>> @@ -638,6 +665,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x10
>>   		>;
>>   	};
>>   
>> +	pinctrl_uart3: uart3grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140
>> +			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140
>> +			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x140
>> +			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
>> +		>;
>> +	};
>> +
>>   	pinctrl_usdhc2: usdhc2grp {
>>   		fsl,pins = <
>>   			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
>> -- 
>> 2.37.1
>>
>>
>>
Marco Felsch Oct. 21, 2022, 9:09 a.m. UTC | #3 
On 22-10-21, Peng Fan wrote:
> Hi Marco,
> 
> On 10/20/2022 7:07 PM, Marco Felsch wrote:
> > Hi Peng,
> > 
> > On 22-10-20, Peng Fan (OSS) wrote:
> > > From: Peng Fan <peng.fan@nxp.com>
> > > 
> > > Enable uart1/3 ports for evk board.
> > > 
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >   arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
> > >   1 file changed, 36 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > index 2e29bb3c041c..366f709f8790 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > @@ -428,6 +428,15 @@ &snvs_pwrkey {
> > >   	status = "okay";
> > >   };
> > > +&uart1 { /* BT */
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pinctrl_uart1>;
> > > +	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
> > > +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
> > 
> > I'm curious, what is the default parent and why is this wrong? For the
> > already exisiting uart2 we don't do that. Same applies for uart3.
> 
> The default parent is OSC_24M. The uart2 is for console, so 24M is ok.
> As I recall, we met issue 24M not able to get higher baudrate.

What did you mean by higher baudrate, is it everything > 115200? When
the console baudrates can be fullfilled with the PLL1_80M as well
wouldn't it be worth to fix the imx8mp.dtsi instead?

Regards,
  Marco
Peng Fan (OSS) Oct. 21, 2022, 9:31 a.m. UTC | #4 
Hi Marco,

On 10/21/2022 5:09 PM, Marco Felsch wrote:
> On 22-10-21, Peng Fan wrote:
>> Hi Marco,
>>
>> On 10/20/2022 7:07 PM, Marco Felsch wrote:
>>> Hi Peng,
>>>
>>> On 22-10-20, Peng Fan (OSS) wrote:
>>>> From: Peng Fan <peng.fan@nxp.com>
>>>>
>>>> Enable uart1/3 ports for evk board.
>>>>
>>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>>> ---
>>>>    arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
>>>>    1 file changed, 36 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
>>>> index 2e29bb3c041c..366f709f8790 100644
>>>> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
>>>> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
>>>> @@ -428,6 +428,15 @@ &snvs_pwrkey {
>>>>    	status = "okay";
>>>>    };
>>>> +&uart1 { /* BT */
>>>> +	pinctrl-names = "default";
>>>> +	pinctrl-0 = <&pinctrl_uart1>;
>>>> +	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
>>>> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
>>>
>>> I'm curious, what is the default parent and why is this wrong? For the
>>> already exisiting uart2 we don't do that. Same applies for uart3.
>>
>> The default parent is OSC_24M. The uart2 is for console, so 24M is ok.
>> As I recall, we met issue 24M not able to get higher baudrate.
> 
> What did you mean by higher baudrate, is it everything > 115200? When
> the console baudrates can be fullfilled with the PLL1_80M as well
> wouldn't it be worth to fix the imx8mp.dtsi instead?

To console, we use 115200, 24M could fullfill it.

BaudRate = (clk / ref_clk_div) / (16 * (ubmr + 1) / (ubir + 1))

If you have 24M ref_clk, the max baudrate is 1.5M, with setting
ubmr, ubir to 0, and ref clk divider to 1.

So more higher baudrate, 24M could not fulfill.

THanks,
Peng.

> 
> Regards,
>    Marco
Marco Felsch Oct. 21, 2022, 9:53 a.m. UTC | #5 
On 22-10-21, Peng Fan wrote:
> Hi Marco,
> 
> On 10/21/2022 5:09 PM, Marco Felsch wrote:
> > On 22-10-21, Peng Fan wrote:
> > > Hi Marco,
> > > 
> > > On 10/20/2022 7:07 PM, Marco Felsch wrote:
> > > > Hi Peng,
> > > > 
> > > > On 22-10-20, Peng Fan (OSS) wrote:
> > > > > From: Peng Fan <peng.fan@nxp.com>
> > > > > 
> > > > > Enable uart1/3 ports for evk board.
> > > > > 
> > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > ---
> > > > >    arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
> > > > >    1 file changed, 36 insertions(+)
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > > > index 2e29bb3c041c..366f709f8790 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > > > @@ -428,6 +428,15 @@ &snvs_pwrkey {
> > > > >    	status = "okay";
> > > > >    };
> > > > > +&uart1 { /* BT */
> > > > > +	pinctrl-names = "default";
> > > > > +	pinctrl-0 = <&pinctrl_uart1>;
> > > > > +	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
> > > > > +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
> > > > 
> > > > I'm curious, what is the default parent and why is this wrong? For the
> > > > already exisiting uart2 we don't do that. Same applies for uart3.
> > > 
> > > The default parent is OSC_24M. The uart2 is for console, so 24M is ok.
> > > As I recall, we met issue 24M not able to get higher baudrate.
> > 
> > What did you mean by higher baudrate, is it everything > 115200? When
> > the console baudrates can be fullfilled with the PLL1_80M as well
> > wouldn't it be worth to fix the imx8mp.dtsi instead?
> 
> To console, we use 115200, 24M could fullfill it.
> 
> BaudRate = (clk / ref_clk_div) / (16 * (ubmr + 1) / (ubir + 1))
> 
> If you have 24M ref_clk, the max baudrate is 1.5M, with setting
> ubmr, ubir to 0, and ref clk divider to 1.
> 
> So more higher baudrate, 24M could not fulfill.

Okay, thanks for clarification. In that case eveything is fine.

Regards,
  Marco
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 2e29bb3c041c..366f709f8790 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -428,6 +428,15 @@  &snvs_pwrkey {
 	status = "okay";
 };
 
+&uart1 { /* BT */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
 &uart2 {
 	/* console */
 	pinctrl-names = "default";
@@ -450,6 +459,15 @@  &usb_dwc3_1 {
 	status = "okay";
 };
 
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
 &usdhc2 {
 	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 	assigned-clock-rates = <400000000>;
@@ -625,6 +643,15 @@  MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
 		>;
 	};
 
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
+			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140
+			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
@@ -638,6 +665,15 @@  MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x10
 		>;
 	};
 
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140
+			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140
+			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x140
+			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
+		>;
+	};
+
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190