| Message ID | 20221023215649.221726-1-m.grzeschik@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: zynqmp: Enable hs termination flag for USB dwc3 controller | expand |
On Sun, Oct 23, 2022 at 11:56:49PM +0200, Michael Grzeschik wrote: >Since we need to support legacy phys with the dwc3 controller, >we enable this quirk on the zynqmp platforms. Gentle Ping! >Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> >--- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > >diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >index a549265e55f6e7..7c1af75f33a05b 100644 >--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >@@ -825,6 +825,7 @@ dwc3_0: usb@fe200000 { > clock-names = "bus_early", "ref"; > iommus = <&smmu 0x860>; > snps,quirk-frame-length-adjustment = <0x20>; >+ snps,resume-hs-terminations; > /* dma-coherent; */ > }; > }; >@@ -851,6 +852,7 @@ dwc3_1: usb@fe300000 { > clock-names = "bus_early", "ref"; > iommus = <&smmu 0x861>; > snps,quirk-frame-length-adjustment = <0x20>; >+ snps,resume-hs-terminations; > /* dma-coherent; */ > }; > }; >-- >2.30.2 > > >
On 10/23/22 23:56, Michael Grzeschik wrote: > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > Since we need to support legacy phys with the dwc3 controller, > we enable this quirk on the zynqmp platforms. > > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index a549265e55f6e7..7c1af75f33a05b 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -825,6 +825,7 @@ dwc3_0: usb@fe200000 { > clock-names = "bus_early", "ref"; > iommus = <&smmu 0x860>; > snps,quirk-frame-length-adjustment = <0x20>; > + snps,resume-hs-terminations; > /* dma-coherent; */ > }; > }; > @@ -851,6 +852,7 @@ dwc3_1: usb@fe300000 { > clock-names = "bus_early", "ref"; > iommus = <&smmu 0x861>; > snps,quirk-frame-length-adjustment = <0x20>; > + snps,resume-hs-terminations; > /* dma-coherent; */ > }; > }; > -- > 2.30.2 > Applied. M
Hello! On 23.10.22 23:56, Michael Grzeschik wrote: > Since we need to support legacy phys with the dwc3 controller, > we enable this quirk on the zynqmp platforms. Slightly off-topic question below. > > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index a549265e55f6e7..7c1af75f33a05b 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -825,6 +825,7 @@ dwc3_0: usb@fe200000 { > clock-names = "bus_early", "ref"; > iommus = <&smmu 0x860>; > snps,quirk-frame-length-adjustment = <0x20>; > + snps,resume-hs-terminations; > /* dma-coherent; */ Is it possible to configure coherent DMA for the device and this is currently not done or how should this comment be interpreted? Thanks! Ahmad > }; > }; > @@ -851,6 +852,7 @@ dwc3_1: usb@fe300000 { > clock-names = "bus_early", "ref"; > iommus = <&smmu 0x861>; > snps,quirk-frame-length-adjustment = <0x20>; > + snps,resume-hs-terminations; > /* dma-coherent; */ > }; > };
Hi, On 11/30/22 18:02, Ahmad Fatoum wrote: > Hello! > > On 23.10.22 23:56, Michael Grzeschik wrote: >> Since we need to support legacy phys with the dwc3 controller, >> we enable this quirk on the zynqmp platforms. > > Slightly off-topic question below. > >> >> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> >> --- >> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> index a549265e55f6e7..7c1af75f33a05b 100644 >> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> @@ -825,6 +825,7 @@ dwc3_0: usb@fe200000 { >> clock-names = "bus_early", "ref"; >> iommus = <&smmu 0x860>; >> snps,quirk-frame-length-adjustment = <0x20>; >> + snps,resume-hs-terminations; >> /* dma-coherent; */ > > Is it possible to configure coherent DMA for the device and this is currently > not done or how should this comment be interpreted? I didn't try it for a while but before you start a53 you can enable CCI and then dma-coherent flags should be enabled. Thanks, Michal
Hello, On 30.11.22 18:08, Michal Simek wrote: > Hi, > > On 11/30/22 18:02, Ahmad Fatoum wrote: >> Hello! >> >> On 23.10.22 23:56, Michael Grzeschik wrote: >>> Since we need to support legacy phys with the dwc3 controller, >>> we enable this quirk on the zynqmp platforms. >> >> Slightly off-topic question below. >> >>> >>> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> >>> --- >>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >>> index a549265e55f6e7..7c1af75f33a05b 100644 >>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >>> @@ -825,6 +825,7 @@ dwc3_0: usb@fe200000 { >>> clock-names = "bus_early", "ref"; >>> iommus = <&smmu 0x860>; >>> snps,quirk-frame-length-adjustment = <0x20>; >>> + snps,resume-hs-terminations; >>> /* dma-coherent; */ >> >> Is it possible to configure coherent DMA for the device and this is currently >> not done or how should this comment be interpreted? > > > I didn't try it for a while but before you start a53 you can enable CCI and then dma-coherent flags should be enabled. I see. Wouldn't this apply to all DMA-capable devices then? So this comment would be better placed top-level in /soc? Also, why did you decide against having cache coherency be the default? I'd expect this to be a performance improvement (if it functions correctly). The Layerscape LS1046A also has a CCI and normal setup is to configure it and have /soc/dma-coherent. Thanks, Ahmad > > Thanks, > Michal >
Hi, On 11/30/22 18:12, Ahmad Fatoum wrote: > Hello, > > On 30.11.22 18:08, Michal Simek wrote: >> Hi, >> >> On 11/30/22 18:02, Ahmad Fatoum wrote: >>> Hello! >>> >>> On 23.10.22 23:56, Michael Grzeschik wrote: >>>> Since we need to support legacy phys with the dwc3 controller, >>>> we enable this quirk on the zynqmp platforms. >>> >>> Slightly off-topic question below. >>> >>>> >>>> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> >>>> --- >>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ >>>> 1 file changed, 2 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >>>> index a549265e55f6e7..7c1af75f33a05b 100644 >>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >>>> @@ -825,6 +825,7 @@ dwc3_0: usb@fe200000 { >>>> clock-names = "bus_early", "ref"; >>>> iommus = <&smmu 0x860>; >>>> snps,quirk-frame-length-adjustment = <0x20>; >>>> + snps,resume-hs-terminations; >>>> /* dma-coherent; */ >>> >>> Is it possible to configure coherent DMA for the device and this is currently >>> not done or how should this comment be interpreted? >> >> >> I didn't try it for a while but before you start a53 you can enable CCI and then dma-coherent flags should be enabled. > > I see. Wouldn't this apply to all DMA-capable devices then? So this comment would be better > placed top-level in /soc? yes of course. > > Also, why did you decide against having cache coherency be the default? > I'd expect this to be a performance improvement (if it functions correctly). I haven't seen such a request to enable it by default but from build perspective you need to do one more additional step which none is really doing. Definitely there is missing code in bootloader which is also sharing the same DT description. I know that we were trying that configuration in past but not sure if this is in regression or if there is any issue with any driver. Thanks, Michal
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index a549265e55f6e7..7c1af75f33a05b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -825,6 +825,7 @@ dwc3_0: usb@fe200000 { clock-names = "bus_early", "ref"; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; + snps,resume-hs-terminations; /* dma-coherent; */ }; }; @@ -851,6 +852,7 @@ dwc3_1: usb@fe300000 { clock-names = "bus_early", "ref"; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; + snps,resume-hs-terminations; /* dma-coherent; */ }; };
Since we need to support legacy phys with the dwc3 controller, we enable this quirk on the zynqmp platforms. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+)