From patchwork Tue Oct 25 09:02:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13018833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BAD1C04A95 for ; Tue, 25 Oct 2022 09:10:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Y9niVUQXWEDPlFr+q2VhI0rCqYBw5hkXJ5ur10VCmOg=; b=dp7HVtRbOmTapc eWWlJY97INLHjWBGUB/9UmOcpVeRvnLKFUyCWpUqS+PQ6r5nWpnZmrDixXazFnPktN4LsZ5dXBRzP st4hWrfL1Ju2QjlxnaQAmDXHeo7BfVxeKo1t8HZKEwrApASqCLiCEBr53dRAA5Nh6/XTTrRWnroz8 UPc2voPKHiwwoofiPRhL9cNSn45rMk5BaXeT50C08/wdFHUnuXstOEJ3HkXNnR9SUAhTMi33+h9TT osinfwPHj3r/LDkPRN3eOsX2+ohulemEaPkjhfD0yYWUiEYR3jYvb5ruiTAQ2T5/K33y+oJyJjTCZ cyzZpsVfD5d6NIXyS2AA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1onFw3-004S8b-DO; Tue, 25 Oct 2022 09:09:24 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1onFqi-004POC-U2 for linux-arm-kernel@lists.infradead.org; Tue, 25 Oct 2022 09:03:54 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666688632; x=1698224632; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mc6SsypKCjut3u6a+plDwQ+qo2GsXn3Mr3PKcaDZdms=; b=UU/lz70iJJqf0AAEAVhLlTmhkWHJkl9laixddfbnR26rIc+Rz9GMr7YG jJByLatq1O6h6UmjnsCkN7N+0JXhIw1rDtITbDqakPL5dsgCUYOVsUjI0 krTn9oWuEvm5mC8lY1r/vPiFSoQZwmwSu/JFmNz8kpz9rg4Anpn9ttzIN JszfVX5DJ2uyepzwbuczkAj5d0gbqEAINIqrCYNyRc2qqaqi7olHXZ2/V htbOPBzjgCqvgVCrTqQ+27sohMJSzXNr3omRnrasllMOgu4XmIj+n465P gPOo/kB5Xq+EiqWaE1sO/vNRJDUICPiRTJY0jmlB18E95nUMmuZfTHDB7 w==; X-IronPort-AV: E=Sophos;i="5.95,211,1661842800"; d="scan'208";a="196910056" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Oct 2022 02:03:51 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 25 Oct 2022 02:03:52 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 25 Oct 2022 02:03:49 -0700 From: Tudor Ambarus To: , , Subject: [PATCH v2 13/32] dmaengine: at_hdmac: Don't allow CPU to reorder channel enable Date: Tue, 25 Oct 2022 12:02:47 +0300 Message-ID: <20221025090306.297886-14-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025090306.297886-1-tudor.ambarus@microchip.com> References: <20221025090306.297886-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221025_020352_992408_F0816F9C X-CRM114-Status: UNSURE ( 9.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tudor Ambarus , maciej.sosnowski@intel.com, linux-kernel@vger.kernel.org, mripard@kernel.org, linux-arm-kernel@lists.infradead.org, dmaengine@vger.kernel.org, stable@vger.kernel.org, torfl6749@gmail.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org at_hdmac uses __raw_writel for register writes. In the absence of a barrier, the CPU may reorder the register operations. Introduce a write memory barrier so that the CPU does not reorder the channel enable, thus the start of the transfer, without making sure that all the pre-required register fields are already written. Fixes: dc78baa2b90b ("dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller") Reported-by: Peter Rosin Signed-off-by: Tudor Ambarus Cc: stable@vger.kernel.org Link: https://lore.kernel.org/lkml/13c6c9a2-6db5-c3bf-349b-4c127ad3496a@axentia.se/ --- drivers/dma/at_hdmac.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index 80eeb4fb88ef..968a5aba47cd 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -256,6 +256,8 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) ATC_SPIP_BOUNDARY(first->boundary)); channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) | ATC_DPIP_BOUNDARY(first->boundary)); + /* Don't allow CPU to reorder channel enable. */ + wmb(); dma_writel(atdma, CHER, atchan->mask); vdbg_dump_regs(atchan);