| Message ID | 20221025113242.58271-2-yangyicong@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add TLP filter support and some fixes for HiSilicon PCIe PMU | expand |
On Tue, 25 Oct 2022 19:32:40 +0800 Yicong Yang <yangyicong@huawei.com> wrote: > From: Yicong Yang <yangyicong@hisilicon.com> > > Some event id of hisi-pcie-pmu is incorrect, fix them. > > Fixes: 8404b0fbc7fb ("drivers/perf: hisi: Add driver for HiSilicon PCIe PMU") > Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> FWIW given these are magic value updates. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/perf/hisilicon/hisi_pcie_pmu.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilicon/hisi_pcie_pmu.c > index 21771708597d..071e63d9a9ac 100644 > --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c > +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c > @@ -693,10 +693,10 @@ static struct attribute *hisi_pcie_pmu_events_attr[] = { > HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_cnt, 0x10210), > HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_latency, 0x0011), > HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_cnt, 0x10011), > - HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x1005), > - HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x11005), > - HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x2004), > - HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x12004), > + HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x0804), > + HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x10804), > + HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x0405), > + HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x10405), > NULL > }; >
diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilicon/hisi_pcie_pmu.c index 21771708597d..071e63d9a9ac 100644 --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c @@ -693,10 +693,10 @@ static struct attribute *hisi_pcie_pmu_events_attr[] = { HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_cnt, 0x10210), HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_latency, 0x0011), HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_cnt, 0x10011), - HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x1005), - HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x11005), - HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x2004), - HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x12004), + HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x0804), + HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x10804), + HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x0405), + HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x10405), NULL };