| Message ID | 20221026015850.591044-4-mranostay@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: add 4x lane support for pci-j721e controllers | expand |
On 26/10/22 7:28 am, Matt Ranostay wrote: > Added dev_warn messages to alert of devicetree misconfigurations > for incorrect num-lanes setting, or the lack of one being defined. > > Signed-off-by: Matt Ranostay <mranostay@ti.com> > --- Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> [...] Regards Vignesh
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 397e456af439..5a3e257055e4 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -442,9 +442,16 @@ static int j721e_pcie_probe(struct platform_device *pdev) pcie->user_cfg_base = base; ret = of_property_read_u32(node, "num-lanes", &num_lanes); - if (ret || num_lanes > data->max_lanes) + if (ret) { + dev_warn(dev, "no num-lanes defined, defaulting to 1\n"); num_lanes = 1; + } + if (num_lanes > data->max_lanes) { + dev_warn(dev, "defined num-lanes %u is greater than the allowed maximum of %u, defaulting to 1\n", + num_lanes, data->max_lanes); + num_lanes = 1; + } pcie->max_lanes = data->max_lanes; pcie->num_lanes = num_lanes;
Added dev_warn messages to alert of devicetree misconfigurations for incorrect num-lanes setting, or the lack of one being defined. Signed-off-by: Matt Ranostay <mranostay@ti.com> --- drivers/pci/controller/cadence/pci-j721e.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)