| Message ID | 20221026055001.12986-8-amit.kachhap@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: Expose Armv8 AArch32 features via hwcap | expand |
On Wed, Oct 26, 2022 at 7:53 AM Amit Daniel Kachhap <amit.kachhap@arm.com> wrote: > Speculation Barrier(FEAT_SB) is a feature present in AArch32 state for > Armv8 and is represented by ISAR6.SB identification register. > > This feature denotes the presence of SB instruction and hence adding a > hwcap will enable the userspace to check it before trying to use this > instruction. > > This commit adds the ID feature bit detection, and uses elf_hwcap2 > accordingly. > > Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> The patch is fine, the following is a question. I see that the aarch64 kernel is using this instruction in the kernel for speculation barriers, and after this the aarch32 userspace can use it too. Does it make sense to ask the question whether this could be compiled into and used by a aarch32 kernel, provided it is configured for a core known to support it? (This is assuming that the compiler also knows about it.) I'm asking because speculation barriers is something we have a lot of due to the constant security problems so it might be something handy to have in the toolbox. It might be just adding too much complexity... I know. Yours, Linus Walleij
On 11/16/22 19:36, Linus Walleij wrote: > On Wed, Oct 26, 2022 at 7:53 AM Amit Daniel Kachhap > <amit.kachhap@arm.com> wrote: > >> Speculation Barrier(FEAT_SB) is a feature present in AArch32 state for >> Armv8 and is represented by ISAR6.SB identification register. >> >> This feature denotes the presence of SB instruction and hence adding a >> hwcap will enable the userspace to check it before trying to use this >> instruction. >> >> This commit adds the ID feature bit detection, and uses elf_hwcap2 >> accordingly. >> >> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> > > The patch is fine, the following is a question. > > I see that the aarch64 kernel is using this instruction in the kernel > for speculation barriers, and after this the aarch32 userspace can > use it too. > > Does it make sense to ask the question whether this could be > compiled into and used by a aarch32 kernel, provided it is > configured for a core known to support it? (This is assuming that > the compiler also knows about it.) I think you have a valid point to use sb in the kernel also. Besides the compiler support, aarch32 kernel might need feature based dynamic instruction patching framework like aarch64. So as you said it is too much to do here. Thanks, Amit Daniel > > I'm asking because speculation barriers is something we have a > lot of due to the constant security problems so it might be something > handy to have in the toolbox. > > It might be just adding too much complexity... I know. > > Yours, > Linus Walleij
On 2022-11-16 14:06, Linus Walleij wrote: > On Wed, Oct 26, 2022 at 7:53 AM Amit Daniel Kachhap > <amit.kachhap@arm.com> wrote: > >> Speculation Barrier(FEAT_SB) is a feature present in AArch32 state for >> Armv8 and is represented by ISAR6.SB identification register. >> >> This feature denotes the presence of SB instruction and hence adding a >> hwcap will enable the userspace to check it before trying to use this >> instruction. >> >> This commit adds the ID feature bit detection, and uses elf_hwcap2 >> accordingly. >> >> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> > > The patch is fine, the following is a question. > > I see that the aarch64 kernel is using this instruction in the kernel > for speculation barriers, and after this the aarch32 userspace can > use it too. > > Does it make sense to ask the question whether this could be > compiled into and used by a aarch32 kernel, provided it is > configured for a core known to support it? (This is assuming that > the compiler also knows about it.) > > I'm asking because speculation barriers is something we have a > lot of due to the constant security problems so it might be something > handy to have in the toolbox. > > It might be just adding too much complexity... I know. Certainly none of Arm's CPUs new enough to implement FEAT_SB still support AArch32 at EL1. Robin.
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h index 46833c668ec2..bc9e7d318e25 100644 --- a/arch/arm/include/uapi/asm/hwcap.h +++ b/arch/arm/include/uapi/asm/hwcap.h @@ -43,5 +43,6 @@ #define HWCAP2_SHA1 (1 << 2) #define HWCAP2_SHA2 (1 << 3) #define HWCAP2_CRC32 (1 << 4) +#define HWCAP2_SB (1 << 5) #endif /* _UAPI__ASMARM_HWCAP_H */ diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index de2d85ddec8d..f676c54e5d14 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -450,6 +450,7 @@ static void __init cpuid_init_hwcaps(void) { int block; u32 isar5; + u32 isar6; if (cpu_architecture() < CPU_ARCH_ARMv7) return; @@ -485,6 +486,12 @@ static void __init cpuid_init_hwcaps(void) block = cpuid_feature_extract_field(isar5, 16); if (block >= 1) elf_hwcap2 |= HWCAP2_CRC32; + + /* Check for Speculation barrier instruction */ + isar6 = read_cpuid_ext(CPUID_EXT_ISAR6); + block = cpuid_feature_extract_field(isar6, 12); + if (block >= 1) + elf_hwcap2 |= HWCAP2_SB; } static void __init elf_hwcap_fixup(void) @@ -1264,6 +1271,7 @@ static const char *hwcap2_str[] = { "sha1", "sha2", "crc32", + "sb", NULL };
Speculation Barrier(FEAT_SB) is a feature present in AArch32 state for Armv8 and is represented by ISAR6.SB identification register. This feature denotes the presence of SB instruction and hence adding a hwcap will enable the userspace to check it before trying to use this instruction. This commit adds the ID feature bit detection, and uses elf_hwcap2 accordingly. Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> --- arch/arm/include/uapi/asm/hwcap.h | 1 + arch/arm/kernel/setup.c | 8 ++++++++ 2 files changed, 9 insertions(+)