| Message ID | 20221026055813.13484-3-amit.kachhap@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Expose compat Armv8 AArch32 features | expand |
On Wed, Oct 26, 2022 at 11:28:07AM +0530, Amit Daniel Kachhap wrote: > These hwcaps are earlier added for 32-bit native arm kernel and hence the > corresponding changes added in 32-bit compat arm64 kernel for similar > userspace interface. Floating point half-precision (FPHP) and Advanced > SIMD half-precision (ASIMDHP) represent the Armv8 FP16 feature extension > and is already advertised in arm64 kernel. Can you provide a pointer to the commit adding these for arch/arm/, please? I've not been able to spot them in linux-next so I'm a bit confused. Will
On 11/9/22 23:30, Will Deacon wrote: > On Wed, Oct 26, 2022 at 11:28:07AM +0530, Amit Daniel Kachhap wrote: >> These hwcaps are earlier added for 32-bit native arm kernel and hence the >> corresponding changes added in 32-bit compat arm64 kernel for similar >> userspace interface. Floating point half-precision (FPHP) and Advanced >> SIMD half-precision (ASIMDHP) represent the Armv8 FP16 feature extension >> and is already advertised in arm64 kernel. > > Can you provide a pointer to the commit adding these for arch/arm/, please? > I've not been able to spot them in linux-next so I'm a bit confused. Those arch/arm/ patches are not merged yet. I only posted in the mailing list. Here is the link to it. http://lists.infradead.org/pipermail/linux-arm-kernel/2022-October/784016.html Thanks, Amit > > Will
On Thu, Nov 10, 2022 at 09:48:59AM +0530, Amit Kachhap wrote: > On 11/9/22 23:30, Will Deacon wrote: > > On Wed, Oct 26, 2022 at 11:28:07AM +0530, Amit Daniel Kachhap wrote: > > > These hwcaps are earlier added for 32-bit native arm kernel and hence the > > > corresponding changes added in 32-bit compat arm64 kernel for similar > > > userspace interface. Floating point half-precision (FPHP) and Advanced > > > SIMD half-precision (ASIMDHP) represent the Armv8 FP16 feature extension > > > and is already advertised in arm64 kernel. > > > > Can you provide a pointer to the commit adding these for arch/arm/, please? > > I've not been able to spot them in linux-next so I'm a bit confused. > > Those arch/arm/ patches are not merged yet. I only posted in the mailing > list. > Here is the link to it. http://lists.infradead.org/pipermail/linux-arm-kernel/2022-October/784016.html We'd need to get the arm32 changes reviewed and merged first before we can take the arm64 compat counterpart.
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 298b386d3ebe..a3f1f5c32c39 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -31,6 +31,8 @@ #define COMPAT_HWCAP_VFPD32 (1 << 19) #define COMPAT_HWCAP_LPAE (1 << 20) #define COMPAT_HWCAP_EVTSTRM (1 << 21) +#define COMPAT_HWCAP_FPHP (1 << 22) +#define COMPAT_HWCAP_ASIMDHP (1 << 23) #define COMPAT_HWCAP2_AES (1 << 0) #define COMPAT_HWCAP2_PMULL (1 << 1) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 43e5b43ef550..1dc06f086b84 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -442,8 +442,8 @@ static const struct arm64_ftr_bits ftr_mvfr0[] = { static const struct arm64_ftr_bits ftr_mvfr1[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0), @@ -2842,6 +2842,8 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), + HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_FPHP_SHIFT, 4, FTR_UNSIGNED, 3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), + HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDHP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 28d4f442b0bc..c19922a7402d 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -143,6 +143,8 @@ static const char *const compat_hwcap_str[] = { [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", + [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp", + [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp", }; #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
These hwcaps are earlier added for 32-bit native arm kernel and hence the corresponding changes added in 32-bit compat arm64 kernel for similar userspace interface. Floating point half-precision (FPHP) and Advanced SIMD half-precision (ASIMDHP) represent the Armv8 FP16 feature extension and is already advertised in arm64 kernel. Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> --- arch/arm64/include/asm/hwcap.h | 2 ++ arch/arm64/kernel/cpufeature.c | 6 ++++-- arch/arm64/kernel/cpuinfo.c | 2 ++ 3 files changed, 8 insertions(+), 2 deletions(-)