From patchwork Fri Oct 28 14:24:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13023758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 945A5ECAAA1 for ; Fri, 28 Oct 2022 14:26:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Kq9e6cxRbTetI7hsCHS9DvTYPeTfagawLfW6a6fzzqM=; b=zf1WFZ8nKRXNqM Yxz5QWzFoe8adYgs8PnczpAoy4NOOEpzHgUdCABGYi4jJVKMZoMFWhh5nJ/tsplgCyiM44Js/e9ZR hsLdiojyO8gtreJ1MpU87AJw9vgXgeQmLworBYONl9/JZb5AXEWnv0GDew3+3olNdlo3LhQuQ8sO4 k3IQbQxATrKcqLGTPjoEsXwTGdP99TX50EuyihzVTrQDn8fe8gJKsi1VfKlE0aNufysy9mcSzeQ29 NwipNQH6VtydbbwlT5MDx9p5ftSu7RkbNKPeQMEKJn6RRC0adf/ljL8COk4KhRbqt82tZB5di1hv+ pYQiA8eLvFalfN3H9UIQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ooQIi-0002V5-QI; Fri, 28 Oct 2022 14:25:37 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ooQHY-00023u-SB for linux-arm-kernel@lists.infradead.org; Fri, 28 Oct 2022 14:24:28 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOLcl023819; Fri, 28 Oct 2022 09:24:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666967061; bh=Co7awRy3Xz2XTZgEsm+7R4njsey9lJWTDZmbVB0K4DA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Hq39yu6FLWt48WmQL03y3it86mUiIZ5oyuizWMGPk10c4R3AHKWD9pycONUCF+5rt sYJsnBuVOeLI7pRkQHpUC6wfFei4SxSMXIgJlbD2g3GXFT0415j+0oSEEyS5/3klz+ ffYib+QAO80fnYa51zqlewEsHc3bWolCn2zgDrZ4= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29SEOK6v062524 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Oct 2022 09:24:20 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 28 Oct 2022 09:24:20 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 28 Oct 2022 09:24:20 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOHfS039275; Fri, 28 Oct 2022 09:24:20 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , Le Jin , Jan Kiszka , CC: , , Andrew Davis Subject: [PATCH 03/11] arm64: dts: ti: k3-am65: Enable SPI nodes at the board level Date: Fri, 28 Oct 2022 09:24:09 -0500 Message-ID: <20221028142417.10642-4-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028142417.10642-1-afd@ti.com> References: <20221028142417.10642-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221028_072425_037172_9FB11C7D X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the SPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + 4 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 945a8a70332e9..fa4b6eb02fa57 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -574,6 +574,7 @@ &usb1 { }; &mcu_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_spi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index feef5fdb46886..74fd807d47396 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -217,6 +217,7 @@ main_spi0: spi@2100000 { #size-cells = <0>; dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; dma-names = "tx0", "rx0"; + status = "disabled"; }; main_spi1: spi@2110000 { @@ -229,6 +230,7 @@ main_spi1: spi@2110000 { #size-cells = <0>; assigned-clocks = <&k3_clks 137 1>; assigned-clock-rates = <48000000>; + status = "disabled"; }; main_spi2: spi@2120000 { @@ -239,6 +241,7 @@ main_spi2: spi@2120000 { power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; main_spi3: spi@2130000 { @@ -249,6 +252,7 @@ main_spi3: spi@2130000 { power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; main_spi4: spi@2140000 { @@ -259,6 +263,7 @@ main_spi4: spi@2140000 { power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; sdhci0: mmc@4f80000 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index dc0f439d2dacb..7a11501bad0bc 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -58,6 +58,7 @@ mcu_spi0: spi@40300000 { power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; mcu_spi1: spi@40310000 { @@ -68,6 +69,7 @@ mcu_spi1: spi@40310000 { power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; mcu_spi2: spi@40320000 { @@ -78,6 +80,7 @@ mcu_spi2: spi@40320000 { power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; tscadc0: tscadc@40200000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 991a8559b4c3b..3f5a5ebfc8f3c 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -342,6 +342,7 @@ &ecap0 { }; &main_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; #address-cells = <1>;