From patchwork Fri Oct 28 16:54:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13024150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C10E4ECAAA1 for ; Fri, 28 Oct 2022 17:23:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=v8ewmGy21jkrJTyK6BkHMnzlGCMiYiSeXl6y9UbCz4M=; b=41uyZx+R8RxPIV QmvsTjxfJ4CWLj7kKrememnw7M75IRGg60gPeOnk2kz1bGSRjAopkG9JudPsM+eWQVMJt8zIsz1th U/LhuJIdbDFIWWsw6+LhAkm6pOa0EKSFXSUuVj/yy7tKyL4wIRIOyyYg5s0lPYMxnSjNuiNNzZLvz fEBaAL3PwJ1lSbNSzFFAc5nJ5bkEGhv0Rz8faq31Q59hcIPgJyF+qJQy5jd9/A/KcmdEaxqw4XuOn Dnt76uj+mThd3sGFbUNgt604809fvaU9m510MHdZrgigOSWsgF59X63pkfw4Bo1DgAXt3IcynbEbC lsaLAK7P3FYFxaHVB5iw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ooT3u-001FnW-CP; Fri, 28 Oct 2022 17:22:30 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ooSdl-0014JE-3G for linux-arm-kernel@lists.infradead.org; Fri, 28 Oct 2022 16:55:30 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3E4131042; Fri, 28 Oct 2022 09:55:35 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 32D183F703; Fri, 28 Oct 2022 09:55:28 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Mark Brown , Will Deacon , James Morse Subject: [PATCH 31/38] arm64/sysreg: Convert ID_PFR2_EL1 to automatic generation Date: Fri, 28 Oct 2022 17:54:19 +0100 Message-Id: <20221028165426.1707896-32-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221028165426.1707896-1-james.morse@arm.com> References: <20221028165426.1707896-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221028_095529_220659_DBA4AE60 X-CRM114-Status: UNSURE ( 9.26 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert ID_PFR2_EL1 to be automatically generated as per DDI0487I.a, no functional changes. Reviewed-by: Mark Brown Signed-off-by: James Morse --- arch/arm64/include/asm/sysreg.h | 4 ---- arch/arm64/tools/sysreg | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 85197dd180e0..ccb64dc09a4e 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -165,7 +165,6 @@ #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) -#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) @@ -694,9 +693,6 @@ #define ID_DFR0_EL1_CopSDbg_SHIFT 4 #define ID_DFR0_EL1_CopDbg_SHIFT 0 -#define ID_PFR2_EL1_SSBS_SHIFT 4 -#define ID_PFR2_EL1_CSV3_SHIFT 0 - #define MVFR0_EL1_FPRound_SHIFT 28 #define MVFR0_EL1_FPShVec_SHIFT 24 #define MVFR0_EL1_FPSqrt_SHIFT 20 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b7c968a4f18e..8a7ea3e84942 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -606,6 +606,22 @@ Enum 3:0 SpecSEI EndEnum EndSysreg +Sysreg ID_PFR2_EL1 3 0 0 3 4 +Res0 63:12 +Enum 11:8 RAS_frac + 0b0000 NI + 0b0001 RASv1p1 +EndEnum +Enum 7:4 SSBS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 3:0 CSV3 + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_AA64PFR0_EL1 3 0 0 4 0 Enum 63:60 CSV3 0b0000 NI