From patchwork Mon Oct 31 09:19:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13025503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70A37FA3740 for ; Mon, 31 Oct 2022 09:21:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Ke5xXVDoiboeECvigvvoA5cA/EgwpgG91pwY8PrdsC0=; b=3DGmKBojCZHF4D DSeHI1kYuBSDLKpapbIj4/uPh1f+Sy2h0CHUThop36Kchs9evhJ52lakYo6U+lXu3mGtTSrsoCivM tiL0aXKoptrLkE70uwr1kxA5lFdM1ndPGnHXIVbL3tgbVYb7MsY2LuNORXusDificY6pi++rU1j9I Ow/TfUW8TgCkeFMpeLCdCmbWDqkZj4tdbHP3N675i04UEx50UvnihrfAD/XUBXSMCe5JDFh5qUun8 0kjaVJdzHIUSFRXz2Cc5KHhz+fF+Br+R1XrQmPe3uuhkLA6fBTe4IxsMkAj2o1UaWxExsUd9uxs3k PTwoA+7RkRTDCi2WHJmg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1opQy6-009z6M-Ka; Mon, 31 Oct 2022 09:20:31 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1opQxS-009ygt-0u for linux-arm-kernel@lists.infradead.org; Mon, 31 Oct 2022 09:19:51 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5754823A; Mon, 31 Oct 2022 02:19:53 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AD2403F703; Mon, 31 Oct 2022 02:19:44 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , Alim Akhtar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 06/20] arm64: dts: Update cache properties for exynos Date: Mon, 31 Oct 2022 10:19:45 +0100 Message-Id: <20221031091945.531874-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221031_021950_155269_4E0DF402 X-CRM114-Status: UNSURE ( 8.32 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois Reviewed-by: Alim Akhtar --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++ arch/arm64/boot/dts/exynos/exynos7.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index bd6a354b9cb5..e9eda46801f8 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -229,6 +229,7 @@ cluster_a57_l2: l2-cache0 { cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; }; cluster_a53_l2: l2-cache1 { @@ -236,6 +237,7 @@ cluster_a53_l2: l2-cache1 { cache-size = <0x40000>; cache-line-size = <64>; cache-sets = <256>; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 1cd771c90b47..aca1c32a6411 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -110,6 +110,7 @@ atlas_l2: l2-cache0 { cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; }; };