From patchwork Mon Oct 31 11:56:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 13025686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8363DFA3740 for ; Mon, 31 Oct 2022 11:57:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=K93rpYVgGxvMEwdq6MYomdSvu50RYWi27GuIIkRApxQ=; b=I4CotzYNsnA1Td LOuPL02R7kojPOt8Itq1inh0NuGt/8iDAfMX43pMDric7GWdFGX3HLwxm67FETqxdK8Pg/qPL+DKf juEEO2+7LqaLqxD33dMLXVbVfMSFPvJfdWpHOyqmzKVCjfYrYLT54GXLzGdoAyCeeG0aJSWVy2lNg IGQoKWWXvypXcXiwX/oBt04dNEWhLkAZNSLJ7ZMaxVES1aBVPUruwpli8EAu5LIScrujZm5/mze0X MTkrEDC5zMgcZb8NLmHzf46eqOxSJaT7SCd/ir5fDT1doS2UKPh4JHRIZETgEV2/cb/uCaTV/6h+q vGF9SVWqKMKWWkr6D1PQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1opTPB-00BTL6-Rg; Mon, 31 Oct 2022 11:56:37 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1opTP0-00BTHV-3y for linux-arm-kernel@lists.infradead.org; Mon, 31 Oct 2022 11:56:27 +0000 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id EE3818218; Mon, 31 Oct 2022 11:46:54 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: Georgi Vlaev , Grygorii Strashko , Keerthy , Ladislav Michl , Nishanth Menon , Suman Anna , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 1/3] clocksource/drivers/timer-ti-dm: Add lock for register access Date: Mon, 31 Oct 2022 13:56:11 +0200 Message-Id: <20221031115613.56229-2-tony@atomide.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221031115613.56229-1-tony@atomide.com> References: <20221031115613.56229-1-tony@atomide.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221031_045626_216784_A240618A X-CRM114-Status: GOOD ( 14.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We currently have no locking for timer control register and we assume that the consumer device using struct omap_dm_timer_ops takes care of locking for the timer. In order to prepare for adding irchip and clock provider support to start removing the struct omap_dm_timer_ops custom API, let's add timer->lock and use it for the timer control register. This is needed to protect the control register access between the different kernel frameworks. Not-Yet-Signed-off-by: Tony Lindgren --- drivers/clocksource/timer-ti-dm.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-ti-dm.c --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -121,6 +121,7 @@ struct dmtimer { int id; int irq; struct clk *fclk; + spinlock_t lock; /* For shared register access */ void __iomem *io_base; int irq_stat; /* TISR/IRQSTATUS interrupt status */ @@ -633,6 +634,7 @@ static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *n static int omap_dm_timer_free(struct omap_dm_timer *cookie) { struct dmtimer *timer; + unsigned long flags; struct device *dev; int rc; @@ -649,7 +651,9 @@ static int omap_dm_timer_free(struct omap_dm_timer *cookie) return rc; /* Clear timer configuration */ + spin_lock_irqsave(&timer->lock, flags); dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0); + spin_unlock_irqrestore(&timer->lock, flags); pm_runtime_put_sync(dev); @@ -728,6 +732,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) static int omap_dm_timer_start(struct omap_dm_timer *cookie) { struct dmtimer *timer; + unsigned long flags; struct device *dev; int rc; u32 l; @@ -742,11 +747,13 @@ static int omap_dm_timer_start(struct omap_dm_timer *cookie) if (rc) return rc; + spin_lock_irqsave(&timer->lock, flags); l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); if (!(l & OMAP_TIMER_CTRL_ST)) { l |= OMAP_TIMER_CTRL_ST; dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); } + spin_unlock_irqrestore(&timer->lock, flags); return 0; } @@ -754,6 +761,7 @@ static int omap_dm_timer_start(struct omap_dm_timer *cookie) static int omap_dm_timer_stop(struct omap_dm_timer *cookie) { struct dmtimer *timer; + unsigned long flags; struct device *dev; unsigned long rate = 0; @@ -766,7 +774,9 @@ static int omap_dm_timer_stop(struct omap_dm_timer *cookie) if (!timer->omap1) rate = clk_get_rate(timer->fclk); + spin_lock_irqsave(&timer->lock, flags); __omap_dm_timer_stop(timer, rate); + spin_unlock_irqrestore(&timer->lock, flags); pm_runtime_put_sync(dev); @@ -800,6 +810,7 @@ static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enable, unsigned int match) { struct dmtimer *timer; + unsigned long flags; struct device *dev; int rc; u32 l; @@ -813,6 +824,7 @@ static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enable, if (rc) return rc; + spin_lock_irqsave(&timer->lock, flags); l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); if (enable) l |= OMAP_TIMER_CTRL_CE; @@ -820,6 +832,7 @@ static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enable, l &= ~OMAP_TIMER_CTRL_CE; dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match); dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); + spin_unlock_irqrestore(&timer->lock, flags); pm_runtime_put_sync(dev); @@ -830,6 +843,7 @@ static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on, int toggle, int trigger, int autoreload) { struct dmtimer *timer; + unsigned long flags; struct device *dev; int rc; u32 l; @@ -843,6 +857,7 @@ static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on, if (rc) return rc; + spin_lock_irqsave(&timer->lock, flags); l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); @@ -854,6 +869,7 @@ static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on, if (autoreload) l |= OMAP_TIMER_CTRL_AR; dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); + spin_unlock_irqrestore(&timer->lock, flags); pm_runtime_put_sync(dev); @@ -887,6 +903,7 @@ static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie, int prescaler) { struct dmtimer *timer; + unsigned long flags; struct device *dev; int rc; u32 l; @@ -900,6 +917,7 @@ static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie, if (rc) return rc; + spin_lock_irqsave(&timer->lock, flags); l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); if (prescaler >= 0) { @@ -907,6 +925,7 @@ static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie, l |= prescaler << 2; } dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); + spin_unlock_irqrestore(&timer->lock, flags); pm_runtime_put_sync(dev); @@ -1093,6 +1112,8 @@ static int omap_dm_timer_probe(struct platform_device *pdev) if (!timer) return -ENOMEM; + spin_lock_init(&timer->lock); + timer->irq = platform_get_irq(pdev, 0); if (timer->irq < 0) return timer->irq;