| Message ID | 20221101141658.3631342-8-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: dts: suniv: F1C100s: add more peripherals | expand |
Dne torek, 01. november 2022 ob 15:16:56 CET je Andre Przywara napisal(a): > The CIR (infrared receiver) controller in the Allwinner F1C100s series > of SoCs is compatible to the ones used in other Allwinner SoCs. > > Add the DT node describing the resources of the controller. > There are multiple possible pinmuxes, but none as them seem to be an > obvious choice, so refrain from adding any pincontroller subnodes for > now. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 2901c586971b4..d29b48f23b89a 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -251,6 +251,17 @@ pwm: pwm@1c21000 { status = "disabled"; }; + ir: ir@1c22c00 { + compatible = "allwinner,suniv-f1c100s-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c22c00 0x400>; + clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&ccu RST_BUS_IR>; + interrupts = <6>; + status = "disabled"; + }; + uart0: serial@1c25000 { compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>;
The CIR (infrared receiver) controller in the Allwinner F1C100s series of SoCs is compatible to the ones used in other Allwinner SoCs. Add the DT node describing the resources of the controller. There are multiple possible pinmuxes, but none as them seem to be an obvious choice, so refrain from adding any pincontroller subnodes for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)